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Int. Conf. Proc.

1

S. Y. Hwang, T. Blank, and K. Y. Choi, 'Incremental Functional Simulation of Digital Circuits',  in Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 392-395, November 1987.

2

S. Y. Hwang, M. Odani, T. Blank, and T. Rokicki, 'The ILSP Behavioral Synthesis System',, presented at ACM/IEEE-CS Workshop on High-Level Synthesis, Eastsound, Washington, January 1988.

3

K. Y. Choi, S. Y. Hwang, and T. Blank, 'Incremental-in-Time Algorithm for Digital Simulation',  in Proc. ACM/IEEE 25th Design Automation Conf., pp. 501-505, June 1988.

4

M. Odani, S. Y. Hwang, and T. Blank, 'Hermod: An Interactive Behavioral Synthesizer for VLSI',  in Proc. Int. Symp.  Circuits and Systems, IEEE, pp. 1871-1874, May 1989.

5

B. S. Lee and S. Y. Hwang, 'Behavioral Optimization in CHDL Silicon Compiler System', in Proc. JTC - CSCC, KITE/IEEE, pp. 290-295, Dec. 1990.

6

H. D. Lee, H. S. Jun, and S. Y. Hwang, 'Datapath Synthesis in Sogang Silicon Compiler',  in Proc. JTC - CSCC, KITE/IEEE, pp. 430-435, Dec. 1990.

7

Y. J. Lee, I. H. Moon, and S. Y. Hwang, 'A Logic/Timing Extractor from Transistor Schematic',  in Proc. Int. Conf. on  VLSI and CAD, KITE/IEEE, pp. 135-138, Oct. 1991.

8

I. H. Moon, Y. J. Lee, and S. Y. Hwang, 'Symbolic Extraction from Hierarchical Layout of Arbitrary Shape', in Proc. Int. Conf. on VLSI and CAD,  KITE/IEEE, pp. 131-134, Oct. 1991.

9

H. S. Jun and S. Y. Hwang, 'Automatic Synthesis of Pipeline Structures with Variable Data Initiation Intervals', in Proc. ACM/IEEE 31st Design Automation Conf., San Diego, California, pp. 537-541, June 1994.

10

M. H. Hyun, S. Y. Hwang, and Y. U. Yu, 'Synthesis of VHDL Sequential Statements at Register Transfer Level',  in Proc. APCHDL'94, Toyohashi, Japan, pp. 243-246, Oct. 1994.

11

J. H. Cho, S. Y. Hwang, and Y. U. Yu, 'An Educational and Learning Kit for VHDL Modeling and ASIC Implementation', in Proc. EDA & T, Oct. 1994.

12

H. D. Lee and S. Y. Hwang, 'A Scheduling Algorithm for Multiport Memory Minimization in Datapath Synthesis', in Proc. ASPDAC/CHDL/VLSI'95,  Chiba, Japan, pp. 93-100, Sept. 1995.

13

S. I. Lim, H. C. Choi, S. H. Lee, S. Y. Hwang, G. S. Kang, S. H. Lee, and M. J. Choe, 'A 10-Bit 20-MHz Three-Stage A/D Converter',  in Proc. Int. Conf. on VLSI and CAD, IEEE/KITE, pp. 139-142, Oct. 1995.

14

S. I. Lim, S. H. Lee, and S. Y. Hwang, 'A 12-Bit 10-MHz 250-mW CMOS A/D Converter', in Proc. Int. Solid-State Circuits Conference, IEEE, San Francisco, CA, pp. 316-317, Feb. 1996.

15

M. H. Hyun, J. H. Na, and S. Y. Hwang, 'Design of a Pipelined Music Synthesizer Based on Wavetable Method',  in Proc. ICCE, IEEE, Chicago, IL, pp. 252-253, June 1997.

   
   
   
 
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