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Int. Journal

1

S. Y. Hwang, R. W. Dutton, and T. Blank, 'A Best-first Search Algorithm for Optimal PLA Folding', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-5, No. 3, pp. 433-442, July 1986.

2

S. Y. Hwang, M. Odani, and T. Blank, 'Fast Functional Simulation: An Incremental Approach', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-7, No. 7, pp. 765-774, July 1988.

3

K. Y. Choi, S. Y. Hwang, and T. Blank,'Incremental Algorithms for Digital Simulation', Integration, the VLSI Journal, North-Holland, Vol. 7, No. 1, pp. 21-34, May 1989.

4

S. Y. Hwang, M. Odani, and T. Blank, 'The Hermod Behavioral Synthesis System',  with M. Odani, T. Blank, T. Rokicki, Journal of Systems and Software, North-Holland/Elsevier Science Pub., Vol. 13, 1990.

5

H. S. Jun and S. Y. Hwang, 'Design of a Pipelined Datapath Synthesis System for Digital Signal Processing',  IEEE Transactions on VLSI Systems, Vol. 2, No. 3, pp. 292-303, September 1994.

6

H. D. Lee and S. Y. Hwang, 'Design of an Area-Efficient Allocation Algorithm for Datapaths with Multi- port Memories', Journal of Microelectronic Systems Integration, Plenum Press : New York/London, Vol. 3, No. 1, pp. 3-17, March 1995.

7

H. S. Jun and S. Y. Hwang, 'Design of a Synthesis System for Pipeline Structures with Variable Data Initiation Intervals', Journal of Microelectronic Systems Integration, Plenum Press : New York/London, Vol. 3, No. 3, pp. 189-203, Sept. 1995.

8

H. S. Jun and S. Y. Hwang, 'Automatic Synthesis of Dynamically Configured Pipelines with Variable Data Initiation Intervals', IEEE Transactions on VLSI Systems, Vol. 4, No. 2, pp. 279-285, June 1996.

9

Y. N. Kim, H. D. Lee, and S. Y. Hwang,'An Interconnect Allocation Algorithm for Performance-driven Datapath Synthesis',  Journal of Circuits, Systems, and Computers, Vol. 6, No. 4, pp. 403-423, Sept. 1996.

10

S. Kim and S. Y. Hwang, 'An Area-Efficient VLSI Architecture for the Traceback Viterbi Decoder Supporting Punctured Codes', Electronics Letters, IEE, Vol. 32, No 8, pp. 733-735, April 1996.

11

H. Heo and S. Y. Hwang, 'An Efficient Algorithm for Untestable Path Detection',  Electronics Letters, IEE, Vol. 32, No. 8, pp. 707-708, April 1996.

12

J. I. Choi, H. S. Jun, and S. Y. Hwang, 'An Efficient Hardware Optimization Algorithm for Fixed-point Digital Signal Processing ASIC Design',  Electronics Letters, IEE, Vol. 32, No. 11, pp. 992-994, May 1996.

13

H. Kim and S. Y. Hwang, 'A Heuristic Algorithm for Low Power Design of Combinational Circuits',  Electronics Letters, IEE, Vol. 32, No. 12, pp. 1066- 1067, June 1996.

14

D. I. Oh and S. Y. Hwang, 'Synchronization Detection in an M-ary PSK System with a Rate-Selectable Punctured Convolutional Code',  with D. Oh, Electronics Letters, IEE, Vol. 32, No. 13, pp. 1173-1175, June 1996.

15

E. J. Hwang, J. H. Lee, S. Kim, M. S. Na, and S. Y. Hwang, 'Design of a Performance-enhanced Traceback Algorithm for the Viterbi Decoder', Electronics Letters, IEE, Vol. 32, No. 14, pp. 1254-1255, July 1996.

16

I. S. Choi, H. Kim, D. W. Seo, and S. Y. Hwang, 'A Kernel-based Precomputation Scheme for the Design of Low-Power Combinational Circuits', Electronics Letters, IEE, Vol. 32, No. 14, pp. 1281-1283, July 1996.

17

J. S. Lee, H. D. Lee, C. W. Park, and S. Y. Hwang, 'A Power-Conscious Scheduling Algorithm for Performance-driven Datapath Synthesis', Electronics Letters, IEE, Vol. 32, No. 17, pp. 1574-1576, Aug. 1996.

18

D. I. Oh, Y. Kim, and S. Y. Hwang, 'A VLSI Architecture of the Trellis Decoding Block for the Digital HDTV Grand Alliance System', IEEE Transactions on Consumer Electronics, Vol. 42, No. 3, pp. 346-356, August 1996.

19

I. S. Choi, H. Kim, D. Seo, and S. Y. Hwang, 'Partitioning-based Algorithm for the Synthesis of Low-power Combinational Circuits', Electronics Letters, IEE, Vol. 32, No. 22, pp. 2041-2042, Oct. 1996.

20

H. D. Lee, J. S. Lee, M. H. Hyun, and S. Y. Hwang, 'An Efficient Synthesis Algorithm for Low-Power ASIC Design', Electronics Letters, IEE, Vol. 32, No. 22, pp. 2060-2062, Oct. 1996.

21

D. I. Oh and S. Y. Hwang, 'Design of a Viterbi Decoder with Low Power Using Minimum- Transition Traceback Scheme', Electronics Letters, IEE, Vol. 32, No. 24, pp. 2198-2199, Nov. 1996.

22

J. S. Lee, H. D. Lee, and S. Y. Hwang, 'A Novel High Level Synthesis Algorithm for Low Power ASIC Design', Journal of Microelectronic Systems Integration, Plenum Press : New York/London, Vol. 4, No. 4, pp. 219-232, Dec. 1996.

23

M. H. Hyun, J. H. Na, and S. Y. Hwang,'Design of a Pipelined Music Synthesizer Based on Wavetable Method', IEEE Transactions on Consumer Electronics, Vol. 43, No. 3, pp. 605-613, Aug. 1997.

24

H. Kim, I. S. Choi, and S. Y. Hwang,'Design of Heuristic Algorithms Based on Shannon Expansion for the Synthesis of Logic Circuits with Low Power',  IEE Proceedings - Circuits, Devices, and Systems, Vol. 144, No. 6, pp. 355-360, Dec. 1997.

25

J. H. Kim, J. S. Yang, and S. Y. Hwang,'Path Sensitization and Gate Sizing Approach to Low Power Optimization', Electronics Letters, IEE, Vol. 34, No. 7, pp. 619-620, April 1998.

26

I. S. Choi and S. Y. Hwang,'A Circuit Partitioning Algorithm for Low Power Design under Area Constraints Using Simulated Annealing', IEE Proceedings - Circuits, Devices, and Systems, Vol. 146, No. 1, pp. 8-15, Feb. 1999.

27

I. S. Choi and S. Y. Hwang, ‘Low-power Logic Synthesis Algorithm Using Multiple Partitioning  under Delay Constraints', Electronics Letters, IEE, Vol. 35, No. 7, pp. 558-560, April 1999.

28

S. J. Kim, J. H. Kim, and S. Y. Hwang, 'An Efficient Algorithm for Glitch Power Reduction', Electronics Letters, IEE, Vol. 35, No. 13, pp. 1040-1041, June 1999.

29

W. K. Paik and S. Y. Hwang, 'DSP Implementation of Real-time MPEG-2 Audio Decoder Using a Novel Synthesis Filter Bank', IEE Electronics Letters, Vol. 35, No. 14, pp. 1128-1130, July 1999.

30

J. K. Choi and S. Y. Hwang, 'Design of an Area-Efficient Pulse-Shaping Interpolation FIR Filter Based on LUT Partitioning', IEE Electronics Letters, Vol. 35, No. 18, pp. 1504-1505, Sept.  1999.

31

W. K. Paik and S. Y. Hwang, 'Design of a Novel Synthesis Filter for Real-time MPEG-2 Decoder Implementation on a DSP Chip', IEEE Transactions on Consumer Electronics, Vol. 45, No. 4, pp. 1119-1129, Nov. 1999.

32

S. Kim, J. Kim, and S. Y. Hwang, 'A New Path Balancing Algorithm for Glitch Power Reduction', with S. Kim and J. Kim, IEE Proceedings - Circuits, Devices, and Systems, Vol. 148, No. 3, pp. 151-156, June 2001.

33

D. H. Kim, S. Kim, and S. Y. Hwang, 'A Novel Turbo Decoder Architecture for Hand-held Communication Devices', IEEE Transactions on Consumer Electronics, Vol. 48, pp. 202-208, May 2002.

34

I. S. Choi, H. Kim, S. I. Lim, and S. Y. Hwang, 'A Kernel-based Partitioning Algorithm for Low-power, Low-area Overhead Circuit Design Using Don't Cares', ETRI Journal, Vol. 24, No. 6, pp. 473-476, Dec. 2002.

35

S. Kim, S. Y. Hwang, and M. Kang, 'A Memory-Efficient Blockwise MAP Decoder Architecture' ETRI Journal, Vol. 26, No. 6, pp. 615-621, Dec. 2004.   

36

H. Choi, Y. Kim, S. Yoo, S.-Y. Hwang, and S.-H. Lee, 'A Programmable 0.8V 10b 60MS/s 19.2mW 0.13um CMOS ADC Operating down to 0.5V' IEEE Transactions Circuits and Systems II, Vol. 55, No. 4, pp. 319-323, April. 2008.

37

W. J. Kim and S. Y. Hwang, 'A Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology,' IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E91-A, No. 11, pp. 3297-3303, Nov. 2008.

38

H. C. Choi, Y. J. Kim, W. J. Kim, Y. L. Kim, and S. H. Lee, 'A 10b 120MS/s 108mW 0.18um CMOS ADC with a PYT-insensitive current reference.' Journal of Analog Integrated Circuits and Signal Processing, Online Published(DOI: 10.1007/s10470-008-9231-4), Nov. 2008.

39

B. E. Kim, J. Y. Chung, and S. Y. Hwang, 'An Efficient Fixed-Point IMDCT Algorithm for High-Resolution Audio Appliances,' IEEE Transactions on Comsumer Electronics, Vol. 54, No. 4, pp. 1867-1872, Nov. 2008

40

W. J. Kim, S. H. Lee, and S. Y. Hwang, 'Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching,' IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,Vol. E92-A, No. 3, pp. 890-899, Mar. 2009.

41

C. S. Park, S. W. Kim, and S. Y. Hwang, 'Design of a Low-area High-throughput LDPC Decoder Using Shared Memory Banks for DVB-S2,' IEEE Transactions on Consumer Electronics, Vol. 55, No. 2, pp. 850-854, May 2009.

42

S. W. Kim, C. S. Park, and S. Y. Hwang, 'Design of a High-Throughput LDPC Decoder for DVB-S2 Using Local Memory Banks,' IEEE Transactions on Consumer Electronics, Vol. 55, No. 3, pp. 1045-1050, Aug. 2009.

43

S.-H. Lee, Y.-C. Yoon, and S. Y. Hwang, 'Communication-Aware Task Assignment Algorithm for MPSoC Using Shared Memory,' Journal of Systems Architecture (Embedded Software Design), Elsevier Pub. Co., Vol.56, Issue 7, pp. 233-241, July 2010.

44

S.-R. Lee, S.-H. Lee, and S. Y. Hwang, 'A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems,' IEICE Transactions on Information and Systems, Vol.93-D, No.8, pp. 2162-2171, Aug 2010.

45

S.-M. Kim, C.-S Park, and S. Y. Hwang, 'A Novel Partially Parallel Architecture for High-throughput LDPC Decoder for DVB-S2,' IEEE Transactions on Consumer Electronics, Vol. 56, No. 2, pp. 820-825, May 2010.

46

S.-H. Lee, H.-M. Park and S. Y. Hwang, 'Motion Image Deblurring Using an Edge Map with Blurred/Noisy Image Pairs,' Optics Communications, Elsevier Pub. Co., Vol. 285, Issue 7, pp. 1777-1786,  April 2012.

47

H. Cho, S. Han, and S. -Y. Hwang, 'Design of an Efficient Real-time Algorithm Using Reduced Feature Dimension for Recognition of Speed Limit Signs,' The Scientific World Journal (Signal Processing),
Vol. 2013, Article ID = 135614, 6 pages, Oct. 2013, doi:10.1155/2013/135614.

48

K. Park and S. -Y. Hwang, 'A Robust Range Estimation with a Monocular Camera for Vision-based Forward Collision Warning System,' The Scientific World Journal (Electronics), Vol. 2014,
Article ID = 923632, 9 pages, Jan. 2014, doi:10.1155/2014/923632.

49

K. Park and S. -Y. Hwang, 'An Improved Haar-like Feature Descriptor for Efficient Object Detection,' Pattern Recognition Letters, Vol. 42C, pp. 148-153, March 2014, http://dx.doi.org/10.1016/j.patrec.2014.02.015.

50

H.Cho and S. -Y. Hwang, 'High-performance On-road Vehicle Detection with Non-biased Cascade Classifier by Weight-Balanced Training,' EURASIP Journal on Image and Video Processing, Vol. 2015, Issue 1, Article ID = 16, June 2015, pp. 1-7.

   
 
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