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Kor. Journal

1

J. S. Yoo and S. Y. Hwang, 'FSM Synthesis from High-Level Descriptions', Journal of the KITE,  Vol. 27, No. 12,  pp. 115-124, Dec. 1990 .

2

I. H. Moon, H. J. Kim and S. H. Oh, 'A Hierarchical and Incremental DRC System Using Sliced-edge Trace Algorithm',  Journal of the KITE,  Vol. 28-A, No. 1,  pp. 60-73, Jan. 1991.

3

J. H. Lee, 'Performance-driven Automatic Logic Synthesis System',  Journal of the KITE,  Vol. 28-A, No. 1, pp. 74-84, January 1991.

4

Y. H. Lee, 'Front-end Design for the Construction of VHDL Design Environment',  Journal of Korea Inform. Sci. Soc.,  Vol. 18, No. 1,  pp. 93-103,  January 1991.

5

H.-S. Jin and I.-H. Moon, 'An Efficient Algorithm for Macro-Cell Placement',  Journal of the KITE,  Vol. 28-A, No. 2,  pp. 164-172,  Feb. 1991.

6

G. J. Lee, 'An Efficient State Assignment Algorithm for Finite State Machines Based on Multi-level Logic',  Journal of Korea Inform. Sci. Soc., Vol. 18, No. 2,  pp. 184-194,  March 1991.

7

T. S. Kim, 'A Rule-based System for Technology Independent Logic Minimization',  Journal of Korea Inform. Sci. Soc.,  Vol. 18, No. 2, pp. 150-161, March 1991.

8

J. H. Lee, 'Fanout-Constrained Logic Synthesis',  Journal of the KITE,  Vol. 28-A, No. 5, pp. 387-397, May 1991.

9

'A Distributed Control Model for Pipelined Data-path Synthesis', KITE Journal of Electronics Engineering,  Vol. 2, No. 1, pp. 96-103, June 1991.

10

H. S. Jun and H. D. Lee, 'Design of the High Level Synthesis System in Sogang Silicon Compiler', Journal of the KITE,  Vol. 28-A, No. 6,  pp. 588-599, June 1991.

11

I. H. Moon and Y. J. Lee, 'Circuit and Symbolic Extraction from VLSI Layouts of Arbitrary Shape', Journal of the KITE, Vol 29-A, No. 1, pp. 48-59, Jan. 1992.

12

T. S. Kim, 'Design of a Technology Mapping System of Logic Circuits',  Journal of the KITE,  Vol. 29-A, No. 2, pp. 88- 99, Feb. 1992 .

13

C. S. Lim, 'Design of Fanin-Constrained Multi-Level Logic Optimization System',  Journal of the KITE,  Vol.29-A, No. 4, pp. 64-73, April 1992 .

14

'Multi-media Data Processing: Algorithm and Hardware', Telecommuni cations Review, Vol. 1, pp. 40-52, Dec. 1991.

15

'Silicon Compilation',  CAD Society Magazine, KITE, Vol. 1, No. 1, pp. 4-12, Jan. 1992.

16

H. S. Jun, 'High-level Synthesis', KITE Review, Vol. 19, No. 1, pp. 55-64, Jan. 1992.

17

'Packet Data Communication in ISDN',  Telecommunications Review, Vol. 2, No. 2, pp. 18-27, Feb. 1992.

18

J. H. Lee and T. S. Kim, 'Logic Synthesis for Silicon Compilation',  KITE Review,  Vol. 19, No. 6,  pp. 34-45  June 1992 .

19

J. H. Song, H. D. Lee, H. S. Jun, 'Design of a Synthesis System for Pipelined Hardware Implementation',  Journal of Korea Inform. Sci. Soc.,  Vol. 20, No. 2,  pp. 178-190,  Feb. 1993 .

20

Y. J. Lee and I. H. Moon, 'Design of a Logic/Timing Extraction System for Higher Level Design Verification', Journal of the KITE, Vol. 30-A, No. 2, pp. 76-85, Feb. 1993.

21

H. D. Lee and H. S. Jun, 'Design of a High-level Synthesis System for VHDL', Journal of Korea Inform. Sci. Soc., Vol. 20, No. 6, pp. 788-801, June 1993 .

22

J. H. Park and H. S. Jun, 'Area Constrained Scheduling for Pipelined Systems Design',  Journal of Korea Inform. Sci. Soc., Vol. 20, No. 6, pp. 862-871, June 1993 .

23

S. B. Kim, 'Implementation of a Layout Generation System for the Gate Matrix Style',  Journal of the KITE,  Vol. 30-A, No. 5, pp. 52-62, May 1993 .

24

H. S. Jun, 'Design of a Pipelined Datapath Synthesis System for Digital Signal Processing', Journal of the KITE,  Vol. 30-A, No. 6, pp. 49-57, June 1993 .

25

Y. H. Lee and H. C. Kim, 'Design of a Multi-level VHDL Simulator',  Journal of the KITE,  Vol. 30-A, No. 10,  pp. 67-76,  Oct. 1993 .

26

I. S. Choi and Y. H. Lee, 'A Study on the Implementation of a Hardware Design Library Server', Journal of the KITE,  Vol. 30-A, No. 12, pp. 125-134, Dec. 1993.

27

W. S. Lim and J. H. Park, 'Design of a Component Library for High-level Synthesis',  Journal of Korea Inform. Sci. Soc.,  Vol. 20, No. 12, pp. 1,867- 1,878, Dec. 1993 .

28

M. S. Jang and J. S. Lee, 'Design of an Automatic Placement System for PCBs', Journal of the KITE,  Vol. 31-A, No. 2, pp. 104-115,  Feb. 1994 .

29

H. J. Lee and J. H. Lee, 'Design of a High-level Synthesis System Supporting Asynchronous Interfaces',  Journal of the KITE,  Vol. 31-A, No. 2, pp. 116- 124, Feb. 1994 .

30

H. D. Lee, 'Design of a High-level Synthesis System for Automatic Generation of Pipelined Datapath',  Journal of the KITE,  Vol. 31-A, No. 3, pp. 53-67,  March 1994 .

31

S. W. Lee, 'Design of a Time Optimized Technology Mapping System', Journal of the KITE, Vol. 31-A, No. 4, pp. 106-115, April 1994.

32

M. H. Hyun, 'Design of an RTL VHDL Synthesis System',  Journal of the KITE,  Vol. 31-A, No. 5,  pp. 149-157,  May 1994 .

33

H. S. Jun, 'Synthesis of Pipeline Structures with Variable Data Initiation Intervals', Journal of the KITE,  Vol. 31-A, No. 6, pp. 149-158, June 1994.

34

H. D. Lee and Y. N. Kim, 'Design of an Automatic Synthesis System for Datapaths Based on Multiport Memories',  Journal of the KITE, Vol. 31-A, No. 7, pp. 117-125, July 1994.

35

E. J. Hwang, J. H. Lee, S. I. Lim, 'Design of Traceback Algorithm for Performance Improvement in Viterbi Decoder',  Journal of the KITE, Vol. 31-A, No. 8, pp. 100-110, August 1994 .

36

I. H. Bae, 'Design of a Neurochip Core with On-chip Learning Capability in Hardware with Minimal Global Control',  Journal of the KITE, Vol. 31-A, No. 10, pp. 161-172, Oct. 1994.

37

J. H. Park and H. S. Jun, 'Design of a Synthesis Algorithm for Multichip Architectures', Journal of the KITE,  Vol. 31-A, No. 12, pp. 122-134, Dec. 1994 .

38

J. H. Lee, C. H. Jang, H. R. Jung, S. Kim, 'VLSI Design of a Digital Signal Processor for Audio Applications',  Journal of Korean Inst. of Comm. Sciences, Vol. 20, No. 5, pp. 1401-1419, May 1995.

39

Y. N. Kim and H. D. Lee, 'An Efficient Interconnect Allocation Algorithm for Clock Period Minimization',  Journal of the KITE, Vol. 32-A, No. 6, pp. 91-103, June 1995.

40

Y. H. Lee, 'Design and Implementation of a VHDL Simulator',  KITE Review, Vol. 22,  No. 8,  pp. 55-75,  Aug. 1995 .

41

H. D. Lee, 'Design of a Datapath Synthesis System for Multiport Memory Minimization', Journal of the KITE, Vol. 32-A, No. 10, pp. 81-92, Oct. 1995.

42

J. I. Choi and H. S. Jun, 'SODAS-DSP: An Automatic Synthesis System Generating Fixed-point Hardwares for Digital Signal Processing',  Telecommunications Review, Vol. 6, No. 1, pp. 86-98, Feb. 1996.

43

C. Jang et al, 'Design of a High-Performance 24-Bit Digital Audio Processor', KITE Journal of Electronics Engineering,  Vol. 7, No. 1, pp. 47-54, March 1996 .

44

H. Kim et al, 'An Efficient Algorithm for the Design of Combinational Circuits with Low Power Consumption', Journal of Korean Institute of Communication Sciences, Vol. 21, No. 5, pp. 1,221-1,229,
May 1996 .

45

D. Oh and Y. Kim, 'VLSI Design of the Trellis Decoder Block for the GA HDTV System', Telecommunications Review, Vol. 6, No. 5, pp. 601-612, Oct. 1996.

46

J. Choi, H. Jun, J. Lee, M. Kim, 'A Bitwidth Optimization Algorithm for Efficient Hardware Sharing', Journal of Korean Institute of Communication Sciences, Vol. 22, No. 3, pp. 454-468, March 1997 .

47

M. H. Hyun, S. K. Lee, C. W. Park, 'Design of a Cosynthesis System for Pipelined Application-Specific Instruction Processors',   Journal of Korean Institute of Communication Sciences, Vol. 22, No. 3,
pp. 444-453, March 1997.

48

H. Heo, 'Design of an Efficient Algorithm for Detection of Untestable Paths in Multi-level Circuits',  Journal of the KITE, Vol. 34-C, No. 3, pp. 11-22, March 1997 .

49

I. S Choi and S. H. Ryu, 'A Kernel-based Precomputation Scheme for Low-power Design of Combinational Circuits', Journal of the KITE, Vol. 34-C, No. 11, pp. 12-19, Nov. 1997.

50

I. S. Choi and H. Kim, 'An Efficient Partitioning-based Algorithm for the Synthesis of Low- power Combinational Circuits',  Journal of Korean Institute of Communication Sciences, Vol. 23, No. 2,
pp. 400-410 ,Feb. 1998 .

51

J. Kim and J. S. Yang, 'Concurrent Gate Sizing and Path Sensitization for Low-Power Design of CMOS Digital Circuits', Journal of KISS (A): Computer Systems and Theory, Vol. 25, No. 7, pp. 777-784, July 1998 .

52

I. S. Choi and H. Kim, 'A Partitioning-based Synthesis Algorithm for the Design of Low- power Combinational Circuits under Area Constraints Using Simulated Annealing', Journal of IEEK (Institute of Electronics Engineers of Korea), Vol. 35-C, No. 7, pp. 46-58, July 1998.

53

J. S. Yang, S. J. Kim, and J. Kim, 'Glitch Reduction through Path Balancing for Low-power CMOS Digital Circuits', Journal of KISS (A): Computer Systems and Theory, Vol. 26, No. 10, pp. 1,275-1,283,
Oct. 1999.

54

S. Y. Hwang, M. S. Yoem, H. S. Yoo, and J. S. Lee, 'Design and Implementation of a Retargetable Instruction-set Simulation Environment for ASIP Design', Telecommunications Review, Vol. 9, No. 6, pp. 1,089-1,106, Nov. 1999.

55

S. Y. Hwang, M. H. Sunwoo, J. D. Cho, and  S. I. Lim, ‘Trend and Prospect for VLSI Design and CAD Technology', IEEK Magazine, Vol. 27, No. 2, pp. 67-82, Feb. 2000.

56

'Gate Sizing and Buffer Insertion Algorithm to Reduce Glitch Power Dissipation', Journal of Electrical Engineering and Information Science, Vol. 5, No. 3, pp. 158-164, June 2000 .

57

H. Kim, S. Choi, K. Chung, and S. Y. Hwang, 'An Efficient Kernel-based Partitioning Algorithm for Low-power, Low-Area Logic Circuit Design', Journal of Korean Institute of Communication Sciences, Vol. 25, No. 8, pp. 1,477-1,486, Aug. 2000 .

58

J. K. Choi, S. Kim, and S. Y. Hwang, 'Design of an Area-Efficient Interpolation FIR Filter Based on LUT Partitioning', Telecommunications Review, SK Telecom, Vol. 10, No. 5, pp. 1,049-1,059, Oct. 2000 .

59

E. B. Han, S. Kim and S. Y. Hwang, 'A Buffer Allocation Algorithm for Memory Minimization in DSP Implementation Based on Fine-grained Model', Telecommunications Review, SK Telecom, Vol. 11, No. 1, pp. 94-112, Feb. 2001.

60

D. H. Kim and S. Y. Hwang, ‘Design of an Efficient Turbo Decoder by Initial Threshold Setting’, Journal of Korean Institute of Communication Sciences, Vol. 26, No. 5B, pp. 582-591, May 2001.

61

M. J. Kang, S. Kim, and S. Y. Hwang, ‘Design of an Area-Efficient Architecture for Block-wise MAP Turbo Decoder’, Journal of Korean Institute of Communication Sciences, Vol. 27, No. 8A,
pp. 725-732, Aug. 2002.

62

J. W. Moon, S. Kim, and S. Y. Hwang, ‘Design of the Normalization Unit for a Low-Power and Area-Efficient Turbo Decoders’, Journal of Korean Institute of Communication Sciences, Vol. 28, No. 11C, Nov. 2003.

63

S. Y. Back, S. Kim, and S. Y. Hwang, ‘Design of a Low Power Turbo Decoder by Reducing Decoding Iterations’, Journal of Korean Institute of Communication Sciences, Vol. 29, No. 1C, Jan. 2004.

64

S. Kim and S. Y. Hwang, ‘Design of an Area-Efficient Survivor Path Unit for Viterbi Decoder Supporting Punctured Code’, Journal of Korean Institute of Communication Sciences, Vol. 29 .2004.

65

H. S. Seo and S. Y. Hwang, ‘A Study on Automatic Interface Generation for Communication between AMBA Bus and IPs’, Journal of Korean Institute of Communication Sciences, Vol. 29, No. 4A,
pp. 390-398, April 2004 .

66

J. J. Choi and S. Y. Hwang, 'Requirements Redundancy and Inconsistency Analysis for Use Case Modeling', Journal of KISS : Software and Applications, Vol. 31, No. 7, pp. 869-882, July 2004.

67

S. H. Lee, J, U. Moon, and S. Y. Hwang, ‘A Study on Automatic Generation of Interface Circuits Based on FSM between Standard Buses and IPs’, Journal of Korean Institute of Communication Sciences, Vol. 30, No. 2A, pp. 137-146, Feb. 2005 .

68

H. J. Lee and S. Y. Hwang, ‘Design of a Low-Power Turbo Decoder Using Parallel SISO Decoders’, Journal of Korean Institute of Communication Sciences, Vol. 30, No. 2C, pp. 25-30, Feb. 2005.

69

J. B. Cho, Y. H. Yoo, and S. Y. Hwang, ‘Construction of an Automatic Generation System of Embedded Processor Cores’, Journal of Korean Institute of Communication Sciences, Vol. 30, No. 6A,
pp. 526-534, June 2005.

70

W. G. Lee and S. Y. Hwang, An Improved Task Scheduling Algorithm for Efficient Dynamic Power Management in Real-Time Systems, Journal of Korean Institute of Communication Sciences, Vol. 31, No. 4A, pp. 393-401, April 2006 .

71

S. H. Lee, K. G. Kang, and S. Y. Hwang, ‘A Study on Automatic Interface Generation by Protocol Mapping’, Journal of Korean Institute of Communication Sciences, Vol. 31, No. 8A, pp. 820-829,
Aug. 2006 .

72

S. R. Lee and S. Y. Hwang, ‘Construction of a Retargetable Compiler Generation System from Machine Behavioral Description’, Journal of Korean Institute of Communication Sciences, Vol. 32, No. 5, pp. 286-294, May 2007.

73

H. C. Kim, S. H. Lee, and S. Y. Hwang, ‘Design of an Integrated Interface Circuit and Device Driver Generation System’, Journal of Korean Institute of Communication Sciences, Vol. 32, No. 6,
pp. 325-333, June 2007 .

74

S. M. Hong, C. S. Park, and S. Y. Hwang, ‘Design of and Automatic Generation System for Cycle-accurate Instruction-set Simulator for DSP Processor’, Journal of Korean Institute of Communication Sciences, Vol. 32, No. 9, pp. 931-939, Sept. 2007 .

75

S. R. Lee and S. Y. Hwang, ‘An Efficient Architecture Exploration Method for Optimal ASIP Design’, Journal of Korean Institute of Communication Sciences,, Vol. 32, No. 9, pp. 913-921, Sept. 2007.

76

J. H. Lee, C. S. Park, and S. Y. Hwang, ‘Design of a Low-Power LDPC Decoder by Reducing Decoding Iteration’, Journal of Korean Institute of Communication Sciences, Vol. 32, No. 9, pp. 801-809,
Sept. 2007.

77

D. W. Kim and S. Y. Hwang, ‘Design of an Automatic Generation System for Embedded Processor Cores with Minimal Power Consumption’, Journal of Korean Institute of Communication Sciences, Vol. 32, No. 10, pp. 1,042-1,050, Oct. 2007 .

78

C. W. Park and S. Y. Hwang, ‘Fast URL Lookup Using URL Prefix Hash Tree’, Journal of Korean Institute of Information Sciences and Engineers, Vol. 35, No. 1, pp. 67-75, Feb. 2008.

79

B. E. Kim and S. Y. Hwang, ‘Implementation of a 16-Bit Fixed-Point MPEG-2/4 AAC Decoder for Mobile Audio Applications’, Journal of Korean Institute of Communication Sciences, Vol. 33, No. 3, pp. 240-246, March 2008.

80

S. H. Lee and S. Y. Hwang, ‘An Area Efficient Network Interface Architecture in NoC’, Journal of Korean Institute of Communication Sciences, Vol. 33, No. 5, pp. 240-246, May 2008.

81

W. J. Kim, S. H. Lee, and S. Y. Hwang, ‘Dynamic Job Distribution Algorithm for Reducing Deadlock & Packet Drop Rate in NoC’, Journal of Korean Institute of Communication Sciences, Vol. 33, No. 7, pp. 528-537, July 2008 .

82

H. C. Kim, S. H. Lee, and S. Y. Hwang, ‘Design of an Automatic Generation System of Device Drivers Using Templates’, Journal of Korean Institute of Communication Sciences, with H. C. Kim and S. H. Lee , Vol. 33, No. 9, pp. 652-660, Sept. 2008 .

83

S. W. Kim, C. S. Park, and S. Y. Hwang, ‘Implementation of High Throughput LDPC Code Decoder for DVB-S2’, Journal of Korean Institute of Communication Sciences, Vol. 33, No. 9, Sept. 2008,
pp. 924-933.

 84

Y.C. Yoon and S. Y. Hwang,Design and Implementation of High-Speed Pattern Matcher in Network Intrusion Detection System', Journal of Korean Institute of Communication Sciences, Vol. 33, No. 11, pp. 1,020-1,029, Nov. 2008.

 85

S.W. Kim and S. Y. Hwang,An Improved Predictive Dynamic Power Management Scheme for Embedded Systems ', Journal of Korean Institute of Communication Sciences, Vol. 34, No. 6,
pp. 641-647, June 2009.

 86

D.Y. Lee and S. Y. Hwang,Design of a Dynamically Reconfigurable Switch for Hybrid Network-on-Chip Systems', Journal of Korean Institute of Communication Sciences, Vol. 34, No. 8, pp. 812-821, Sept. 2009 .

 87

T.H. Yoon, K.S. Kim and S. Y. Hwang,Design of an Efficient FTL Algorithm for Flash Memory Accesses Using Sector-level Mapping', Journal of Korean Institute of Communication Sciences, Vol. 34, No. 12, pp. 1,418-1,425, Dec. 2009.

 88

B. S. Suh and S. Y. Hwang,An Energy-Efficient Task Scheduling Algorithm for Multi Processor Embedded System by Laxity Estimation', Journal of Korean Institute of Communication Sciences, Vol. 35, No. 11, pp. 1,631-1,639, Nov. 2010.

 89

S. W. Kim and S. Y. Hwang,An Efficient Architecture Exploration for Embedded Core Design Exploiting Design Hierarchy', Journal of Korean Institute of Communication Sciences, Vol. 35, No. 12, pp. 1,758-1,765, Dec. 2010.

 90

B. H. Kang, H. M. Cho, J. Y. Kim, K. S. Kim, and S. Y. Hwang,Design of a Real-time Algorithm for the Recognition of Speed Limit Signs Using DCT Coefficients', Journal of Korean Institute of Communication Sciences, Vol. 35, No. 12, pp. 1,766-1,774, Dec. 2010.

 91

S. W. Kim and S. Y. Hwang,Construction of a Compiled-code Simulator Generation System for Efficient Design Exploration in Embedded Core Design', Journal of Korean Institute of Communication Sciences, Vol. 36, No. 1, pp. 71-79, Jan. 2011.

 92

S. J. Hong and S. Y. Hwang,Design of an Efficient FTL Algorithm Exploiting Locality Based on Sector-level Mapping', Journal of Korean Institute of Communication Sciences, Vol. 36, No. 7,
pp. 818-826, Jul. 2011.

 93

K. Y. Park and S. Y. Hwang,An Improved Normalization Method for Haar-like Features for Real-time Object Detection ', Journal of Korean Institute of Communication Sciences, Vol. 36, No. 8,
pp. 505-515, Aug. 2011.

 94

S. W. Han , H. M. Cho, K. S. Kim, and S. Y. Hwang, 'Design of a Real-time Algorithm Using Block-DCT for the Recognition of Speed Limit Signs', Journal of Korean Institute of Communication Sciences, Vol. 36, No. 12, pp. 1,574-1,585, Dec. 2011.

 95

H. M. Cho, W. J. Kang, K. S. Kim, and S. Y. Hwang, '지능형 자동차 구현을 위한 표지판 인식 기술', Korea Information Processing Society Review, Vol. 19, No. 03, pp. 35-44, May 2012.

 96

D. J. Kim, T. H. Oh, and S. Y. Hwang, 'An Improved Phase Estimation Method for AM Range Measurement System', Journal of Korean Institute of Communication Sciences, Vol. 37C, No. 6,
pp. 453-461, June 2012.

 97

D. H. Hwang and S. Y. Hwang, Construction of an Automatic Instruction-Set Extension System for Efficient ASIP Design', Journal of Korean Institute of Communication Sciences, Vol. 38B, No. 1,
pp. 1-9, Jan. 2013.

 98

H. C. Lee and S. Y. Hwang, Design and Implementation of an Automatic Embedded Core Generation System using Advanced Dynamic Branch Prediction', Journal of Korean Institute of Communication Sciences, Vol. 38B, No. 1, pp. 10-17, Jan. 2013.

99

B. W. Chung, K. Y. Park and S. Y. Hwang, 'A Fast and Efficient Haar-Like Feature Selection Algorithm for Object Detection', Journal of Korean Institute of Communication Sciences, Vol. 38A, No. 6,
pp. 486-491, June 2013.

100

I. S. Hwang and S. Y. Hwang, 'An Improved Dynamic Branch Predictor by Selective Access of a Specific Element in 4-Way Cache', Journal of Korean Institute of Communication Sciences,
Vol. 38A, No. 12,  pp. 1,094-1,101, Dec. 2013.

101

W. J. Kang and S. Y. Hwang, 'A Test Wrapper Design to Reduce Test Time for Multi-Core SoC', Journal of Korean Institute of Communication Sciences, Vol. 39B, No. 1, pp. 1-7, Jan. 2014.

102

D. H. Kim and S. Y. Hwang, 'An Efficient Wear-Leveling Algorithm for NAND Flash SSD with Multi-Channel and Multi-Way Architecture', Journal of Korean Institute of Communications Society,
Vol. 39B, No. 7, pp. 425-432, July 2014.

103

M. J. Jeon and S. Y. Hwang, 'Design and Implementation of High-Speed Pattern Matcher Using Multi-Entry Simultaneous Comparator in Network Intrusion Detection System', Journal of Korean Institute of Communications and Information Sciences, Vol. 40, No. 11, pp.2169-2177, Nov. 2015

104

H.-L. Li and S. Y. Hwang, 'An Efficient Page-Level Mapping Algorithm for Handling Write Requests in the Flash Translation by Exploiting Temporal Locality', Journal of Korean Institute of Communications and Information Sciences, Vol. 41, No. 10, pp. 1167-1175, Oct. 2016

105

I. -S. Kim and S. Y. Hwang, 'An Effective Online Training Algorithm by Partitioning Bounding Box for Visual Object Tracking Using Convolutional Neural Network', Journal of Korean Institute of Communications and Information Sciences, Vol. 42, No. 6, pp. 1117-1128, June 2017.
   

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