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[90] Woo Young Choi and Jang Woo Lee, “Improved Hetero-Gate-Dielectric Tunnel Field-Effect Transistors," International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, to be presented.

 

[89] In Eui Lim, Heesauk Jhon, Gyuhan Yoon, Jang Woo Lee, and Woo Young Choi, “Bias-Dependent On-Current Modeling of Short-Channel PMOSFETs with Hot-Carrier Stress Effects," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Gyeongju, Korea, pp. 258-261, July. 3-5, 2017.

 

[88] [Invited] Woo Young Choi, “Monolithic 3D (M3D) Reconfigurable Logic Applications Using Extremely-Low-Power Electron Devices," China Semiconductor Technology International Conference (CSTIC), Shanghai, China, pp. I-7, Mar. 12-13, 2017.

 

[87] Woo Young Choi, “Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Circuits for Low-Power and High-Speed Reconfigurable Logic (RL) Applications," The 5th Korea-EU Workshop on Nanotechnology, Seoul, Korea, pp. 24-25, Oct. 6, 2016.

 

[86] [Invited] Woo Young Choi, “Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Circuits for Low-Power and High-Speed Reconfigurable Logic (RL) Applications," International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, pp. 7-8, Sep. 26-29, 2016.

 

[85] Woo Young Choi, Song Hun Choi, Jang Woo Lee, and In Huh, “Drain-Bias Dependency on Statistical Variability for Tunnel Field-Effect Transistors," International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, pp. 53-54, Sep. 26-29, 2016.

 

[84] Woo Young Choi, Song Hun Choi, Jang Woo Lee, and In Huh, “Influence of Line-Edge Roughness (LER) on Multiple-Gate (MG) Tunnel Field-Effect Transistors (TFETs)," International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, pp. 701-702, Sep. 26-29, 2016.

 

[83] Jang Woo Lee, Jong Han Park and Woo Young Choi, “Triple-gate tunnel FETs encapsulated with an epitaxial layer for high current drivability," 2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Hakodate, Japan, pp. 454-457, Jul. 4-6, 2016.

 

[82] Yong Jun Kim, Hyug Su Kwon and Woo Young Choi, “Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed CMOS-NEM Hybrid Reconfigurbal Logic," 2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Hakodate, Japan, pp. 482-484, Jul. 4-6, 2016.

 

[81] Ho Moon Lee and Woo Young Choi, “Mutually-actuated-nano-electromechanical (MA-NEM) memory switches for low operation voltage," 2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Hakodate, Japan, pp. 380-382, Jul. 4-6, 2016.

 

[80] Sang Wan Kim, Heesauk Jhon and Woo Young Choi, “Miniature CMOS Low Noise Amplifier in 0.18-um Mixed-Signal (Twin-Well) CMOS Process," ITC-CSCC 2015, Seoul, Korea, pp. 40, Jun.29 - Jul. 2, 2015.

 

[79] Jang Woo Lee, and Woo Young Choi, “Random Telegraph Noise Model of Tunnel Field-Effect Transistors," Nano Korea 2015 Symposium, Seoul, Korea, pp. 67, Jul. 1-3, 2015.

 

[78] In Huh, and Woo Young Choi, “Effects of Source Doping Concentration on the Subthreshold Swing (SS) of Tunneling Field-Effect Transistors (TFETs)," Nano Korea 2015 Symposium, Seoul, Korea, pp. 65, Jul. 1-3, 2015.

 

[77] Jong Han Park, and Woo Young Choi, “Esaki-Tunneling-Assisted Tunnel Field-Effect Transistors (ETFETs) for Extremely-Low-Power Applications," Nano Korea 2015 Symposium, Seoul, Korea, pp. 65, Jul. 1-3, 2015.

 

[76] Sang Wan Kim, Seongjae Cho, Jand Hyun Kim, Byung-Gook Park, and Woo Young Choi, "Improvement of On-Off Ratio in Vertical Electron-Hole Bilayer Tunnel Field-Effect Transistors (V-EHBTFETs)," International Conference on Electronics, Information and Communication, Singapore, pp.367-377, Jan. 28-31, 2015.

 

[75] Tae-Ho Lee, Young-Jun Kwon, Jae-Gwan Kim, Sung-Kun Park, In-Wook Cho, Kyung-Dong Yoo, Ji-song Lim, Da-Som Kim, Woo Young Choi, and Gyu-Han Yoon, "Charge Trap Length Dependence and Transconductance Characteristics of a 2T SONOS Cell," 14th Non-Volatile Memory Technology Symposium (NVMTS 2014), Jeju, Korea. pp. 195-196 , Oct. 27-29, 2014. 

 

[74] Sang Wan Kim, Woo Young Choi, Hyun Woo Kim, Jang Hyun Kim, Euyhwan Park, Junil Lee, Taehyung Park, and Byung-Gook Park, “Investigation on Transient Response in Tunnel Field-Effect Transistors (TFETs) Depending on Device Geometric Parameters,” NANO Korea, Seoul, Korea, p. P1401_080, Jul. 1-3, 2014.

 

[73] Sang Wan Kim, Woo Young Choi, Jang Hyun Kim, Hyun Woo Kim, Euyhwan Park, Junil Lee, Taehyung Park, and Byung-Gook Park, “Vertical Structured Electron-Hole Bilayer Tunnel Field-Effect Transistors (V-EHBTFETs) for Complementary Logic Applications,” NANO Korea, Seoul, Korea, p. P1401_079, Jul. 1-3, 2014.

 

[72] Jaesung Jo, Hyunjae Lee, Hyun-Yong Yu, Woo Young Choi, and Changhwan Shin, “Fabriciation of a Ferroelectric Capacitor for Sub-60mV/dec CMOS Devices," 2014 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kanazawa, Japan, pp. 32-34, July. 1-3, 2014. 

 

[71] Dasom Kim, Gyu Han Yun, and Woo Young Choi, “Influence of Electron and Hole Distribution on SONOS Memory Cells," 2014 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kanazawa, Japan, pp. 93-95, July. 1-3, 2014. 

 

[70] Wooyoung Cheon, and Woo Young Choi, “Nonvolatile Memory Applications of Tunneling Field-Effect Transistors," 2014 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kanazawa, Japan, pp. 90-92, July. 1-3, 2014. 

 

[69] Yong Jun Kim, Jun Geun Kang, Byungin Lee, Gyu-Seog Cho, Sung-Kye Park, and Woo Young Choi, "Abnormal Cell-to-Cell Interference of NAND Flash Memory," 2013 International Conference on Solid State Devices and Materials, Fukuoka, Japan, Sep. 25-27, 2013.

[68] Jae Hwan Han, Jiyong Song, and Woo Young Choi, “Stiction-Induced Release voltage Shift of Nano-Electro-Mechanical (NEM) Memory Cells," Nano Korea 2013 Symposium, Seoul, Korea, O1309-001, Jul. 10-12, 2013. 


[67] Jae Hwan Han, Kwanyong Kim, and Woo Young Choi, “Interference of Nano-Electro-Mechanical Memory Cells," 2013 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Seoul, Korea, pp. 143-144, Jun. 26-28, 2013. 

 

[66] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Threshold voltage adjustment method of tunneling field-effect transistors,” International Conference on Electronics, Information and Communication (ICEIC), Bali, Indonesia, pp. 247-248, Jan. 30-Feb. 2, 2013.

 

[65] [Invited] Woo Young Choi, "Tunneling Field-Effect Transistors for Sub-0.5-V Operation," SEMICON Korea 2013 - SEMI Technology Symposium (STS), Seoul, Korea, p. S3-3, Jan. 30-31, 2013. 


[64] Jae Hwan Han, Jiyong Song, and Woo Young Choi, "Investigation of Stiction Effects in Nano-Electro-Mechanical (NEM) Memory Cells Based on Finite Element Analysis (FEA)," 12th Non-Volatile Memory Technology Symposium (NVMTS 2012), Sentosa, Singapore. pp. 101-102 , Oct. 31- Nov. 2, 2012. 

 

[63] Jun Geun Kang, Boram Han, Kyoung-Rok Han, Sung Jae Chung, Gyu-Seog Cho,Sung-Kye Park, and Woo Young Choi,  "Dependency of NAND Flash Memory Cells on Random Dopant Fluctuation (RDF) Effects," 12th Non-Volatile Memory Technology Symposium (NVMTS 2012),  Sentosa, Singapore. pp. 107-108 , Oct. 31- Nov. 2, 2012. 


[62] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Design improvement of L-shaped tunneling field-effect transistors," IEEE International SOI Conference, pp. 4.1-, Oct. 2012. 

 

[61] Sang Wan Kim, Woo Young Choi, Won Bo Shim, Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Study on the ambipolar behavior depending on the length of gate-drain overlap," International Technical Conference on Circuits/Systems, Computers and Communications, pp. P-T3-09-, Jul. 2012. 
 

[60] Sang Wan Kim, Woo Young Choi, Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Investigation on hump effects of L-shaped tunneling field-effect transistors," Silicon Nanoelectronics Workshop, pp. 169-170, Jun. 2012.
 

[59] Min Su Han, Yeong Hwan Kim, Kyung Soo Kim, Jae Min Lee, Youngcheol Oh, Woo Young Choi, and Il Hwan Cho, “Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory," 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Okinawa, Japan, pp. 183-185, Jun. 27-29, 2012. 

[58] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Investigation and optimization of the n-channel and p-channel L-shaped tunneling field-effect transistors," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Okinawa, Japan, pp. 36-37, Jun. 27-29, 2012

 

[57] Jun Geun Kang, Boram Han, Chung Sung Jae, Seok-Kiu Lee, Sung-Kye Park, Gyu-Seog Cho, Kyoung-Rok Han and Woo Young

Choi, “Effects of Random Dopant Fluctuations on NAND Flash Memory Cells,” 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Okinawa, Japan, pp. 48-49, Jun. 27-29, 2012. 

 

[56] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "Ambipolar Behabior of  L-shaped Tunneling Field-Effect Transistros," International Conference on Electronics, Information and Communication, pp. 285-286, Feb. 1-3, 2012. 

 

[55] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "L-Shaped Tunneling Field-Effect Transistors (TFETs) for Low Subthreshold Swing and High Current Drivability," 24th International Microprocesses and Nanotechnology Conference, Kyoto, Japan, pp. 26C-4-5L, Oct. 24-27, 2011.

 

[54] Jae Sung Lee, Woo Young Choi, and In Man Kang, "Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling FETs," 24th International Microprocesses and Nanotechnology Conference, Kyoto, Japan, pp. 26C-4-6, Oct. 24-27, 2011. 

 

[53] [Invited] Woo Young Choi, "Nano-Electromechanical (NEM) Memory Cells for Highly Energy-Efficient Systems," IEEE Nanotechnology Materials and Devices Conference 2011, Jeju, Korea, pp. 32-37, Oct. 18-21, 2011. 

 

[52] Gibong Lee and Woo Young Choi, "Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)," 2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Daejeon, Korea, pp. 84-86, Jun. 29-Jul. 1, 2011. 

 

[51] Boram Han and Woo Young Choi, "Analysis of Model of Fringe Field Effect in Nano-Electromechanical (NEM) Nonvolatile Memory," 2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Daejeon, Korea, pp. 277-279, Jun. 29-Jul. 1, 2011.

 

[50] [Invited] Woo Young Choi, "Nano-Electromechanical (NEM) Nonvolatile Memory for Low-Power Electronics," 2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Tokyo, Japan, pp. 5-6, Jun. 30 - Jul. 2, 2010.

 

[49] Min Jin Lee and Woo Young Choi, "Investigation of Abnormal Drain Current Increase of Tunneling Field-Effect Transistors," 2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Tokyo, Japan, pp. 55-56, Jun. 30 - Jul. 2, 2010. 

 

[48] Seung Hyeun Roh and Woo Young Choi, "New Method for Evaluating the Scaling Trend of Nano-Electro-Mechanical (NEM) Nonvolatile Memory Cells," 2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Tokyo, Japan, pp. 231-232, Jun. 30 - Jul. 2, 2010. 

 

[47] Kwangseok Lee and Woo Young Choi, "Multi-Bit Electromechanical Memory Cell for Simple Fabrication Process," IEEE 2010 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 47-48, Jun. 13-14, 2010. 

 

[46] Jung-Shik Jang and Woo Young Choi, "Ambipolarity Characterization of Tunneling Field-Effect Transistors," IEEE 2010 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 135-136, Jun. 13-14, 2010. 

 

[45] Woo Young Choi, "Comparative Study of Tunnel FETs and MOSFETs for Low-Power Consumption," 2009 International Conference on Solid State Devices and Materials, Sendai, Japan, Oct. 7-9, 2009. 

 

[44] Woojun Lee and Woo Young Choi, "Quantitative Analysis of Hump Effects of Multi-Gate MOSFETs for Low-Power Electronics," 2009 International Conference on Solid State Devices and Materials, Sendai, Japan, Oct. 7-9, 2009.

 

[43] Woojun Lee and Woo Young Choi, "Novel Capacitorless DRAM Cell for Low Voltage Operation and Long Data Retention Time," 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, 3B.6, Jun. 24-26, 2009. 

 

[42] Woojun Lee and Woo Young Choi, "A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement," IEEE 2009 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 67-68, Jun. 13-14, 2009. 


[41] Woo Young Choi, Hei Kam, Donovan Lee, Joanna Lai, and Tsu-Jae King Liu, “Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration,” International Electron Devices Meeting (IEDM), Washington, DC, USA, pp. 603-606, Dec. 10-12, 2007. 

 

[40] Jong Pil Kim, Jae Young Song, Sang Wan Kim, Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "30-nm Asymmetric NMOSFET Using a Novel Fabrication Method", IEEE 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 89-90, Jun. 10-11, 2007. 

 

[39] Sang Wan Kim, Woo Young Choi, Jae Young Song, Jong Pil Kim, Junsoo Kim, Hyoungsoo Ko, Hongsik Park, Chulmin Park, Seungbum Hong, Sung-Hoon Choa, Jong Duk Lee, Hyungcheol Shin,  and Byung-Gook Park, "Analysis and Modeling of Resistive Probes", IEEE Nanotechnology Materials and Devices Conference 2006, Gyeongju, Korea, pp. 318-319, Oct. 22-25, 2006. 

 

[38] Woo Young Choi, Jae Young Song, Jong Pil Kim, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, "Breakdown Voltage Reduction in I-MOS Devices", IEEE Nanotechnology Materials and Devices Conference 2006, Gyeongju, Korea, pp. 380-381, Oct. 22-25, 2006. 

 

[37] Hoon Jeong, Yeun Seung Lee, Sangwoo Kang, Il Han Park, Woo Young Choi, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, "Capacitorless DRAM Cell with Highly Scalable Surrounding  Gate Structure," 2006 International Conference on Solid State Devices and Materials, pp.574-575,  Yokohama, Japan, Sep. 13-15, 2006.

 

[36] Woo Young Choi, Jae Young Song, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Multi-Functionality of Novel Structured Tunneling Devices," 2006 International Conference on Solid State Devices and Materials, pp.824-825, Yokohama, Japan, Sep. 13-15, 2006. 

 

[35] Jae Young Song, Woo Young Choi, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Novel  Gate-All-Around MOSFETs with Self-Aligned Structure," 2006 International Conference on Solid State Devices and Materials, pp.1072-1073, Yokohama, Japan, Sep. 13-15, 2006. 

 

[34] [Invited] Byung-Gook Park, Woo Young Choi, Kyung Rok Kim,"Inter-band tunneling and its  application to nanoscale silicon devices : TFET, FITET and MOSFET," International Symposium on the Physics of Semiconductors and Applications 2006, Jeju, Korea, pp.10, Aug. 22-25, 2006. 

 

[33] [Invited] Byung-Gook Park, Woo Young Choi, and Jong Duk Lee,"Characterization and Design Consideration of I-MOS Devices," International Technical Conference on Circuits/Systems, Computers and Communications 2006,Thailand, pp. III_693-III_696, Jul. 10-13, 2006. 

 

[32] Kwon-chil Kang, Sangwoo Kang, Jin Ho Kim, Hong Sun Yang, Woo Young Choi, Gil Seong Lee, Jong Duk Lee, and Byung-Gook Park, "An Approach to a Small Dot Fabricated with an Etch-back Process," International Technical Conference on Circuits/Systems, Computers and Communications 2006,Thailand, pp. I_37-I_40, Jul. 10-13, 2006.

 

[31] Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sangwoo Kang, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, "Design and Simulation of Asymmetric MOSFETs," 2006 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Japan, pp. 175-178, Jul. 3-5, 2006. 

 

[30] Jae Young Song, Woo Young Choi, Jong Pil Kim, Sang Wan Kim, Doo-Hyun Kim, Jin Ho Kim, Dong-Wook Park, Jong Duk Lee, and Byung-Gook Park, "Effects on Multi-Fin on Self-Aligned Gate-All-Around MOSFETs," 2006, Mongolia, pp. 21-24, Jun. 27-28, 2006.

 

[29] Ju Hee Park, Woo Young Choi, Jae Young Song, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Double-Gate SOI FinFETs Using Sidewall Multi-Line Patterning Technique,” IEEE 2006 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 145-146, Jun. 11-12, 2006.

 

[28] Jong Pil Kim, Woo Young Choi, Jae Young Song, Ju Hee Park, Jong Duk Lee, and Byung-Gook Park, "Design and Fabrication of Asymmetric MOSFETs Using a Sidewall Spacer,” IEEE 2006 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 139-140, Jun. 11-12, 2006. 

 

[27] Jae Young Song, Woo Young Choi, Ju Hee Park, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Effects of Oversized Bottom Gate in Self-Aligned Gate-All-Around MOSFET ,” IEEE 2006 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 47-48, Jun. 11-12, 2006. 

 

[26] Woo Young Choi, Byung Yong Choi, Ju Hee Park, Dong-Won Kim, Choong-Ho Lee, Donggun Park, Jong Duk Lee, Young June Park, and Byung-Gook Park, "25nm Programmable Virtual Source/Drain MOSFETs Using a Twin SONOS Memory Structure," International Semiconductor Device Research Symposium, Bethesda, U.S.A., Dec. 7~9, 2005. 

 

[25] Woo Young Choi, Jae Young Song, Jong Duk Lee, Young June Park, and Byung-Gook Park, "70-nm Impact-Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs)," International Electron Devices Meeting, Washington, DC, U.S.A., pp. 975-978, Dec. 5~7, 2005.

 

[24] Jong Duk Lee, Woo Young Choi, Byung-Gook Park, "Challenges in Nanoscale Devices and Breakthrough," 2005 IEEE National Symposium on Microelectronics,Kuching, Malaysia, pp. A1-A5, Nov. 21-24, 2005. 

 

[23] Woo Young Choi, Jae Young Song, Ju Hee Park, Jong Duk Lee, Young June Park, and Byung-Gook Park, "Effect of Substrate Doping Concentration on I-MOS Characteristics," IEEE 2005 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 46-47, Jun. 12-13, 2005.

 

[22] Jae Young Song, Woo Young Choi, JuHee Park, Jong Duk Lee, Young June Park, and Byung-Gook Park, "Optimization of GAA MOSFET Structure and Comparison with DG MOSFETs," IEEE 2005 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 70-71, Jun. 12-13, 2005. 

 

[21] Woo Young Choi, Jae Young Song, Byung Yong Choi, Jong Duk Lee, Young June Park, and Byung-Gook Park, "80nm Self-Aligned Complementary I-MOS Using Double Sidewall Spacer and Elevated Drain Structure and Its Applicability to Amplifiers with High Linearity," International Electron Devices Meeting, San Francisco, U.S.A., pp. 203-206, Dec. 13~15, 2004. 

 

[20] Byung Yong Choi, Yong Kyu Lee, Woo Young Choi, Il Han Park, Hyungcheol Shin, Jong Duk Lee, Byung-Gook Park, Sung Taek Kang, Chilhee Chung, and Donggun Park, "Programmable Virtual Source/Drain MOSFETs," 34th European Soild-State Device Research Conference, Leuven, Belgium, pp. 229-232, Sep. 21-23, 2004.

 

[19] Byung Yong Choi, Yong-Kyu Lee, Woo Young Choi, Il Han Park, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Nano-scale MOSFETs with Programmable Virtual Source/Drain,” 62nd Annual Device Research Conference, pp. 213-214, Indiana, USA, Jun. 21-23, 2004. 

 

[18] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "A New Fabrication Method for Self-aligned Nanoscale I-MOS (Impact-ionization MOS),” 62nd Annual Device Research Conference, pp. 211-212, Indiana, USA, Jun. 21-23, 2004. 

 

[17] Woo Young Choi, Dong-Soo Woo, Byung Yong Choi, Jong Duk Lee, and Byung-Gook Park, "A Novel Biasing Scheme for the I-MOS (Impact-Ionization MOS),” IEEE 2004 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 61-62, Jun. 13-14, 2004.

 

[16] Byung Yong Choi, Woo Young Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "INverted-Sidewall and Partially-Etched Channel (INSPEC) MOSFET on Fully Depleted SOI Substrates,” IEEE 2004 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 31-32, Jun. 13-14, 2004. 

 

[15] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Myeong Won Lee, Jong Duk Lee, and Byung-Gook Park, "A New Stable Extraction of Threshold Voltage Using Regularization Method," Int'l Conf. on Solid State Devices and Materials 2003, pp.420-421,Tokyo, Japan, Sep. 16-18, 2003. 

 

[14] Woo Young Choi, Jong Duk Lee, Byung-Gook Park, "Reverse-Order Source/Drain Formation with Double Offset Spacer (RODOS) for CMOS Low-power, High-Speed and Low-Noise Amplifiers," 2003 International Symposium on Low Power Electronics and Design (ISLPED 2003), pp.189-192, Seoul, Korea, Aug. 25-27, 2003.

 

[13] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design," 2003 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, pp. 5-8, Jun. 30-Jul. 2, 2003. 

 

[12] Myeong Won Lee, In Man Kang, Byung Yong Choi, Dong-Soo Woo, Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "Juncion Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide," 2003 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, pp. 5-8, Jun 30-Jul. 2, 2003. 

 

[11] Dong-Soo Woo, Byung Yong Choi, Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "Self-Aligned FinFET with Large Source/Drain Fan-Out Strucure", IEEE 2003 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 22-23, Jun. 8-9, 2003. 

 

[10] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Sub-50nm MOSFET with Reverse-Order Source/Drain with Double Offset Spacer (RODOS)”, IEEE 2003 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 22-23,Jun. 8-9, 2003. 

 

[9] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "A New Linearity Measurement Algorithm for Sub-Micron Microwave CMOS," 20th IEEE Instrumentation and Measurement Technology Conference, Vail Colorado, USA, pp. 374-376, May 20-22, 2003. 

 

[8] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Stable Extraction of Threshold Voltage Using Transconductance Change Method," 203rd ECS Meeting, Paris, France, Abstract # 27, Apr. 27-May 2, 2003.

 

[7] Jong Duk Lee, Woo Young Choi, Byung Yong Choi, Young Jin Choi, Dong-Soo Woo, and Byung-Gook Park, "30 nm MOSFET Development Based on Processes for Nanotechnology," 2002 IEEE International Conference on Semiconductor Electronics (ICSE2002), pp. 251-254, Penang, Malaysia, Dec. 19-21, 2002. 

 

[6] Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Electrical Characteristics of of FinFET with Vertically Non-Uniform S/D Doping Profile”, IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 23-24, Jun. 9-10, 2002. 

 

[5] Young Jin Choi, Byung Yong Choi, Dong-Soo Woo, Kyung Rok Kim, Woo Young Choi, Cheon Ahn Lee, Jong Duk Lee, and Byung-Gook Park, "A New Side-gate nMOSFET with 50nm Gate Length”, IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 13-14, Jun. 9-10, 2002. 

 

[4] Woo Young Choi, Byung Yong Choi, Jong Duk Lee, and Byung-Gook Park, "Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs," Int'l Conf. on Solid State Devices and Materials 2001, pp.154-155, Tokyo, Japan, Sep. 26-28, 2001.

 

[3] Byung Yong Choi, Woo Young Choi, Young Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Design of 50nm MOSFETs with Biased Side-Gates," 31th European Solid-State Device Research Conference, pp.287-290, Nuremberg, Germany, Sep. 11-13, 2001.

 

[2] Woo Young Choi, Suk Kang Sung, Kyung Rok Kim, Jong Duk Lee, and Byung-Gook Park, ”Nanoscale Poly-Si Line Formation and Its Uniformity,” 2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp. 11-16, Cheju, Korea, Jul. 4-7, 2001. 

 

[1] Byung Yong Choi, Woo Young Choi, Young Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs,” 2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp. 49-54, Cheju, Korea, Jul. 4-7, 2001. 

 

 

Domestic

 

[47] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, and Byung-Gook Park, "Enhanced compact model for Ge-Si heterojunction double-gate tunnel field-effect transistors (TFETs)," NANO Korea, pp. P1701_0654, Jul. 12-14, 2017. 

[46] [Invited] Woo Young Choi, "Nano-Electromechanical (NEM) Devices for Extreme Environments," The Korean Physical Society (KPS) Spring Meeting, Daejeon, Korea, p.F2.04, Apr. 10-21, 2017.

[45] Ho Moon Lee and Woo Young Choi, "Release Voltage Modeling for Nano-Electromechanical (NEM) Memory Switches", Nano Convergence Conference2017, Seoul, Korea, p. 182 , Feb. 22-23, 2017.

 

[44] Tae Min Cha and Woo Young Choi, "Nano-Electromechanical-(NEM-) Memory-Based Field-Programmable Gate Arrays (FPGAs)", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 278 , Feb. 13-15, 2017.

 

[43] Tae Min Cha and Woo Young Choi, "Nano-Electromechanical (NEM) Relay Design Using CMOS Back-End-of-Line (BEOL) Process", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 278 , Feb. 13-15, 2017.

 

[42] In Huh and Woo Young Choi, "Influence of Temperature and Doping Concentration on the Energy Filtering Effects of Tunnel Field-Effect Transistors", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 33 , Feb. 13-15, 2017.

 

[41] Ho Moon Lee and Woo Young Choi, "Switching Voltage Modeling of Nano-Electromechanical (NEM) Memory Switches", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 32 , Feb. 13-15, 2017.

 

[40] Jang Woo Lee and Woo Young Choi, "Hump Effect of Triple-Gate Tunnel FETs Encapsulated with an Epitaxial Layer (EL TFETs)", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 15 , Feb. 13-15, 2017.

 

[39] Hyung Su Kwon, Sangmoo Choi, Sung-Yong Chung, Gyu-Seog Cho, Sung-Kye Park and Woo Young Choi, "Intercell Trapped Charge (ITC) Suppression of Vertical NAND (VNAND) Flash Memory", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 48 , Feb. 13-15, 2017.

 

[38] Heesauk Jhon and Woo Young Choi, "0.3-V supply Charge pump circuit for 65 nm CMOS", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 199 , Feb. 22-24, 2016.

 

[37] Seung Kyu Kim and Woo Young Choi, "Fabrication and Characteristics of Low-Power Device Switches", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 198 , Feb. 22-24, 2016.

 

[36] Seung Kyu Kim and Woo Young Choi, "Fabrication and Characteristics of Low-Power Device Inverters", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 198 , Feb. 22-24, 2016.

 

[35] Hyug Su Kwon, Hyunseung Yoo, Gyu-Seong Cho, Sung-Kye Park and Woo Young Choi, "Novel Degradation of Vertical NAND (VNAND) Flash Memory Cells", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 50 , Feb. 22-24, 2016.

 

[34] In Eui Lim, Heesauk Jhon, Gyuhan Yoon, Byung Kil Choi, Heung Sik Park, Seok Kiu Lee and Woo Young Choi, "Bias-Dependent On-Current Modeling of Ultra Short-Channel PMOSFETs with Hot-Carrier Stress Effects", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 20 , Feb. 22-24, 2016.

 

[33] Woo Young Cheon, Jangwoo Lee, and Woo Young Choi, "Improved Hetero-Gate-Dielectric Tunnel Field-Effect Transistors", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 18 , Feb. 22-24, 2016.

 

[32] [Invited] Woo Young Choi, "Next-Generation Electron Devices for Extremely-Low-Power Applications," Nano Convergence Conference, Seoul, Korea, p. 42 , Jan. 21-22, 2016.

 

[31] Kyung Min Choi, Seung Kyu Kim, and Woo Young Choi, "Work-function Variation and Random Dopand Fluctuation of Tunneling Field-Effect Transistros(TFETs)", The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.

 

[30] Jae Hwan Han, Yong Jun Kim, Tae Min Cha, and Woo Young Choi, "Zigzag Multi-Bit Nano-Electromechanical Memory Cells," The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.

 

[29] Woo Young Cheon, and Woo Young Choi, "Nonvolatile Memory Application of Tunneling Field-Effect Transistors," The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.

 

[28] Da Som Kim, Tae Ho Lee, Young Jun Kwon, Sung Kun Park, In Wook Cho, Kyung Dong Youu, Gyu Han Yun, and Woo Young Choi, "Influence of Electron and Hole Distribution on Embedded SONOS Nonvolatile Memory," The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.

 

[27] Yong Jun Kim, and Woo Young Choi, "Comparison between CMOS and Nano-Electromechanical (NEM) Switches," The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.

 

[26] Jae Hwan Han, Hyunjin Lee, Wansoo Kim, Gyuhan Yoon, and Woo Young Choi, "On-State Resistance Instability of Antifuses during Read Operation," The 21th Korean Conference on Semiconductors, Seoul, Korea, p. 431, Feb. 24-26, 2014.

 

[25] 임지송, 최우영, 윤규한, 이태호, 권영준, 박성근, 조인욱, 유경동, "2T-SONOS 셀의 Endurance 특성고찰," 대한전자공학회 하계종합학술대회, 제주시, 대한민국, pp. 88-91, Jul. 3-5, 2013.

 

[24] Hyun Kook Lee and Woo Young Choi, "Linearity Analysis of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," The 20th Korean Conference on Semiconductors, Hoengseong, Korea, TH3-G-2, Feb, 4-6, 2013. 

 

[23] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, and Byung-Gook Park, "Study on the corner effect of L-shaped tunneling field-effect transistors," NANO Korea, pp. O1201_010-, Aug. 2012. 

 

[22] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "터널링 장벽의 폭이 터널링 전계 효과 트랜지스터의 특성에 미치는 영향에 대한 연구," 하계종합학술대회, pp. 138-141, Jun. 27-29, 2012. 

 

[21] [Invited] Woo Young Choi, "고에너지 효율 시스템 구현을 위한 나노전기기계 소자," 하계종합학술대회, pp. ix, Jun. 27-29, 2012. 

 

[20] [Invited] Woo Young Choi, " Tunneling Field-Effect Transistors: The Next-Generation Devices," The 19th Korean Conference on Semiconductors, Seoul, Korea, p. 336, Feb. 15-17, 2012. 

 

[19] Boram Han and Woo Young Choi, " Analysis of Fringe Field Effects in Nano-Electromechanical (NEM) Nonvolatile Memory Cells," The 19th Korean Conference on Semiconductors, Seoul, Korea, pp. 481-482, Feb. 15-17, 2012. 

 

[18] Kwangseok Lee and Woo Young Choi, "Disturbance Characteristics of Nano-Electromechanical (NEM) Memory Cell (T Cell)," The 18th Korean Conference on Semiconductors, Jeju, Korea, pp. 518-519, Feb. 16-18, 2011. 

 

[17] Seung Hyeun Roh and Woo Young Choi, "Scaling of Nano-Electro-Mechanical System (NEMS) Nonvolatile Memory Cells Based on Finite Element Analysis (FEA)," The 17th Korean Conference on Semiconductors, Daegu, Korea, pp. 288-289, Feb. 24-26, 2010.

 

[16] Woojun Lee and Woo Young Choi, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs) for High Performance and Low-Power Consumption," The 17th Korean Conference on Semiconductors, Daegu, Korea, pp. 49-50, Feb. 24-26, 2010.

 

[15] Woo Young Choi, "Novel Electromechanical Nonvolatile Memory Cell (H Cell) for Multi-Bit Operation," The 17th Korean Conference on Semiconductors, Daegu, Korea, pp. 9-10, Feb. 24-26, 2010. 

 

[14] Woo Young Choi, "Design Guideline and Scalability of Nano-Electro-Mechanical Non-Volatile Memory (NEMory) Cells," The 16th Korean Conference on Semiconductors, Daejeon, Korea, pp. 575-576, Feb. 19-20, 2009. 

 

[13] [Invited] 최우영, "차세대 CMOS 소자," 2006년도 대한전자공학회 추계종합학술대회, 서울시, pp. 9-10, 11 29, 2008. 

 

[12] 최우영, 송재영, 김종필, 김상완, 이종덕, 박병국, "Reduction of Breakdown Voltage in I-MOS Devices," 2006년도 대한전자공학회 하계종합학술대회, 제주도, pp. 593-594, 06 21-23, 2006.

 

[11] 김종필, 최우영, 송재영, 김상완, 이종덕, 박병국, "Design and Simulation of Asymmetric MOSFETs," 2006년도 대한전자공학회 하계종합학술대회, 제주도, pp. 577-578, 06 21-23, 2006.

 

[10] Woo Young Choi, Jae Young Song, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "I-MOS Devices with High ON/OFF Current Ratio and Its integration with TFETs," The 13th Korean Conference on Semiconductors, Jaeju Island, Korea, pp. 101-102, Feb. 23-24, 2006.

 

[9] Woo Young Choi, Jae Young Song, Ju Hee Park, Hoon Jung, Byung Yong Choi, Jong Duk Lee, Young Jun Park, and Byung-Gook Park, "Fabrication of a 100nm n-Channel I-MOS and Its Electrical Characteristics," The 12th Korean Conference on Semiconductors, Seoul, Korea, pp. 101-102, Feb. 24-25, 2005.

 

[8] H. S. Min, Y. J. Park, B. G. Park, S. Jin, W. Choi, S. Hong and R. Kim, "NANOCAD for Modeling and Simulation of Nano Scale and RF MOSFETs," The 1st Workshop on the Emerging Technologies of Semiconductors, Jeju, Korea, pp. 16-17, Oct. 21, 2004.

 

[7] W. Y. Choi and B.-G. Park, "20nm Planar nMOSFETs Using nanofabrication Technologies," The 1st Workshop on the Emerging Technologies of Semiconductors, Jeju, Korea, pp. 114-115, Oct. 21, 2004.

 

[6] Woo Young Choi, Hwi Kim, Dong-Soo Woo, Byung Yong Choi, Byoungho Lee, Jong Duk Lee, and Byung-Gook Park, "A New Stable Threshold Voltage Extraction Method Using the Regularization Theory," The 11th Korean Conference on Semiconductors, Seoul, Korea, vol. 2, pp. 205-206, Feb. 19-20, 2004. 

 

[5] Dong-Soo Woo, Jihye Kong, Hyun Ho Kim, Woo Young Choi, Byung Yong Choi, Jong Duk Lee, Byung-Gook Park, "Low Resistance 30nm Self-Aligned FinFET," The 11th Korean Conference on Semiconductors, Seoul, Korea, vol. 2, pp. 203-204, Feb. 19-20, 2004.

 

[4] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design," The 10th Korean Conference on Semiconductors, Seoul, Korea, pp. 309-310, Feb. 27-28, 2003. 

 

[3] Woo Young Choi, Byung Yong Choi, Young Jin Choi, Dong-Soo Woo, Suk-Kang Sung, Cheon An Lee, Kyung-Hoon Chung, Jong Duk Lee, and Byung-Gook Park, "Development of Ultra-Fine Process Technologies and Their Application to 30nm nMOSFETs," The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 61-62, Feb. 21-22, 2002. 

 

[2] Young Jin Choi, Byung Yong Choi, Dong-Soo Woo, Kyung Rok Kim, Woo Young Choi, Cheon Ahn Lee, Jong Duk Lee, and Byung-Gook Park, "A New 50nm nMOSFET with Side-Gates for Virtual Source/Drain Extension," The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 65-66, Feb. 21-22, 2002. 

 

[1] Dong Soo Woo, Jong Ho Lee, Woo Young Choi, Byung Yong Choi, Young Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Design of Self-Aligned Double-Gate MOSFET with Low Source/Drain Resistance," The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 573-574, Feb. 21-22, 2002. 

 

 
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