Login
Journal

 

TIDL annual achievement

 

 

[110] Sangwan Kim and Woo Young Choi, "Compact Potential Model for Si1-xGex/Si Heterojunction Double-Gate Tunnel Field-Effect Transistors (TFETs)," Journal of Nanoscience and Nanotechnology, to be published. [SCIE]

[109] In Eui Lim, Heesauk Jhon, Gyuhan Yoon, and Woo Young Choi, "On-Current Modeling of Sub-70-nm PMOSFETs Dependent on Hot-Carrier Stress Bias Conditions," Journal of Semiconductor Technology and Science, to be published. [SCIE]

[108] Hyug Su Kwon, Seung Kyu Kim, and Woo Young Choi, "Monolithic Three-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation," IEEE Electron Device Letters, vol. 38, no. 9, pp. 1317-1320, Sep. 2017. [SCI]

[107] In Huh, Sangchun Park, Mincheol Shin, and Woo Young Choi, "An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs ," IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3502-3507, Aug. 2017. [SCI]

[106] Sangwan Kim and Woo Young Choi, "Improved compact model for double-gate tunnel field-effect transistors
by the rigorous consideration of gate fringing field," Japanese Journal of Applied Physics, vol. 56, no. 8, pp. 084301, Jul. 2017. [SCI]

[105] Jang Woo Lee and Woo Young Choi, "Triple-Gate Tunnel FETs Encapsulated with an Epitaxial Layer for High Current Drivability," Journal of Semiconductor Technology and Science, vol. 17, no. 2, pp. 271-276, Apr. 2017. [SCIE]

[104] Ho Moon Lee and Woo Young Choi, "Mutually-Actuated-Nano-Electromechanical (MA-NEM) Memory Switches for Scalability Improvement," Journal of Semiconductor Technology and Science, vol. 17, no. 2, pp. 199-203, Apr. 2017. [SCIE]

[103] Seung Kyu Kim and Woo Young Choi, "Monolithic three-dimensional (M3D) tunnel FET (TFET) - nanoelectromechanical (NEM) hybrid reconfigurable logic circuits," Japanese Journal of Applied Physics, vol. 56, no. 4S, pp. 04CD12, Mar. 2017. [SCI]  

[102] In Eui Lim, Heesauk Jhon, Gyuhan Yoon, and Woo Young Choi, "Drain-Current Modeling of Sub-70-nm PMOSFETs
Dependent on Hot-Carrier Stress Bias Conditions," Journal of Semiconductor Technology and Science, vol. 17, no. 1, pp. 94-100, Feb. 2017. [SCIE]

[101Woo Young Choi, "Influence of line-edge roughness (LER) on multiple-gate (MG) tunnel field-effect transistors (TFETs)," Japanese Journal of Applied Physics, vol. 56, no. 4S, pp. 04CD06, Feb. 2017. [SCI]

[100Woo Young Choi, Hyug Su Kwon, Yong Jun Kim, Byungin Lee, Hyunseung Yoo, Sangmoo Choi, Gyu-Seog Cho, and Sung-Kye Park, "Influence of Intercell Trapped Charge (ITC) on Vertical NAND (VNAND) Flash Memory," IEEE Electron Device Letters, vol. 38, no. 2, pp. 164-167, Feb. 2017. [SCI] 

[99Woo Young Choi, "Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors," Japanese Journal of Applied Physics, vol. 56, no. 4S, pp. 04CD01, Jan. 2017. [SCI]

[98] Hee-Sauk Jhon, Jongwook Jeon, Myunggon Kang, and Woo Young Choi, "A sub-0.5 V operating RF-Low Noise Amplifier using tunneling-FET (TFET)," Japanese Journal of Applied Physics, vol. 56, no. 2, pp. 020303, Jan. 2017. [SCI]

[97] Woo Young Choi, Da Som Kim, Tae Ho Lee, Young Jun Kwon, Sung-Kun Park, and Gyuhan Yoon , "Influence of Electron and Hole Distribution on 2T SONOS Embedded NVM," Journal of Semiconductor Technology and Science, vol. 16, no. 5, pp. 624-629, Oct. 2016. [SCIE]

[96] Jang Woo Lee and Woo Young Choi, "Random Telegraph Noise Model of Tunnel Field-Effect Transistors," Journal of Nanoscience and Nanotechnology, vol. 16, no. 10, pp. 10264-10267, Oct. 2016. [SCIE]

[95] In Huh and Woo Young Choi, "Influence of the Source Doping Concentration on the Subthreshold Swing (SS) of Tunneling Field-Effect Transistors (TFETs)," Journal of Nanoscience and Nanotechnology, vol. 16, no. 10, pp. 10241-10246, Oct. 2016. [SCIE]

[94] Jong Han Park and Woo Young Choi, "Esaki-Tunneling-Assisted Tunnel Field-Effect Transistors for Sub-0.7-V Operation," Journal of Nanoscience and Nanotechnology, vol. 16, no. 10, pp. 10237-10240, Oct. 2016. [SCIE]

[93] Sang Wan Kim and Woo Young Choi, "Hump Effects of Germanium / Silicon Heterojunction Tunnel Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 2583-2588, Jun. 2016. [SCI]

[92] Woo Young Choi and Hyun Kook Lee, "Demonstration of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)," Nano Convergence, vol. 3, no. 1, pp. 1-15, Jun. 2016.

[91] Woo Young Choi, Jae Hwan Han, and Tae Min Cha, Multi-Bit Nano-Electromechanical Nonvolatile Memory Cells (Zigzag T Cells) for the Suppression of Bit-to-Bit Interference," Journal of Nanoscience and Nanotechnology, vol. 16, no. 5, pp. 5164-5167, May 2016. [SCI]

[90] Kyoung Min Choi, Seung Kyu Kim, and Woo Young ChoiInfluence of Number Fluctuation and Position Variation of Channel Dopants and Gate Metal Grains on Tunneling Field-Effect Transistors (TFETs)," Journal of Nanoscience and Nanotechnology, vol. 16, no. 5, pp. 5255-5258, May 2016. [SCI]

[89] In Huh, Woo Young Cheon, and Woo Young Choi, "Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation," Applied Physics Letters , vol. 108, p.153506, Apr. 2016. [SCI]

[88] Woo Young Choi, "Miller effect suppression of tunnel field-effect transistors (TFETs) using capacitor neutralization," IET Electronics Letters, vol. 52, no. 8, pp. 659-661, Apr. 2016. [SCI]

[87] Sang Wan Kim, Jang Hyun Kim, Tsu-Jae King Liu, Woo Young Choi, and Byung-Gook Park, "Demonstration of L-Shaped Tunnel Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 63, no. 4, pp. 1774-1778, Apr. 2016. [SCI]

[86] Seung Kyu Kim and Woo Young ChoiImpact of gate dielectric constant variation on tunnel field-effect transistors (TFETs)," Solid-State Electronics, vol. 116, no. 2, pp. 88-94, Feb. 2016. [SCI]

[85] Jong Han Park and Woo Young Choi, "IoT용 초저전력 터널링 트랜지스터 소자 기술," The Magazine of IEIE, vol.43, no.1, pp. 18-23, Jan. 2016.

[84] Woo Young ChoiDesign Guidelines of Tunneling Field-Effect Transistors for the Suppression of Work-Function Variation," IET Electronics Letters, vol. 51, no. 22, pp. 1819-1821, Nov. 2015. [SCI]

[83] Woo Young Choi and Yong Jun Kim, Three-Dimensional Integration of Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Reconfigurable Circuits," IEEE Electron Device Letters, vol. 36, no. 9, pp. 887-889, Sep. 2015. [SCI]

[82] Song Hun Choi and Woo Young Choi, "차세대 저전력 터널링 트랜지스터," The Magazine of IEIE, vol.42, no.7, pp. 630-635, Jul. 2015.

[81] Jaesung Jo, Woo Young Choi, Jung-Dong Park, Jae Won Shim, Hyun-Yong Yu, and Changhwan Shin, “Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices," Nano Letters, vol. 15, no. 7, pp. 4553-4556, Jul. 2015. [SCI]

[80] Kyoung Min Choi, Wonsok Lee, Keun-Ho Lee, Young-Kwan Park, and Woo Young Choi“Influence of Preferred Gate Metal Grain Orientation on Tunneling Field-Effect Transistors (TFETs)," IEEE Transactions on Electron Devices, vol. 62, no. 4, pp. 1353-1356, Apr. 2015. [SCI]

[79] Woo Jin Jeong, Tae Kyun Kim, Jung Min Moon, Min Gyu Park, Young Gwang Yoon, Byeong Woon Hwang,  Woo Young Choi, Mincheol Shin, and Seok-Hee Lee, “Germanium Electron-Hole Bilayer Tunnel Field-Effect Transistors with a Symmetrically Arranged Double Gate," Semiconductor Science and Technology, vol. 30, no. 3, pp. 035021, Mar. 2015. [SCI]

[78] Eui-Young Song, Jaebum Cho, Hwi Kim,  Woo Young Choi, and Byoungho Lee, “Double bi-material contilever structures for complex surface plasmon modulation," Optics Express, vol. 23, no. 5, pp. 5500-5507, Mar. 2015. [SCI]

[77] Yong Jun Kim and Woo Young ChoiNonvolatile Nano-Electromechanical (NEM) Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays (FPGAs)," IEEE Transactions on Electron Devices, vol. 62, no. 2, pp. 673-679, Feb. 2015. [SCI]

[76] Byeong-In Choe, Jung-Kyu Lee, Bora Lee, Kwanyong Kim, Woo Young Choi, Byung Hee Hong, and Jong-Ho Lee, Fabrication and Electrical Characterization of Graphene Formed Chemically on Nickel Nano Electro Mechanical System (NEMS) Switch," Journal of Nanoscience and Nanotechnology, vol. 14, no. 12, pp.9418-9424, Dec. 2014. [SCI]

[75] Jae Hwan Han, Jiyong Song, and Woo Young ChoiScale effects on stiction-induced release voltage shift of nano-electromechanical (NEM) memory cells," Journal of Nanoscience and Nanotechnology, vol. 14, no. 12, pp.9589-9593, Dec. 2014. [SCI]

[74] Boram Han, Ji Yong Song, and Woo Young Choi, “ Influence of Fringe Field on Nano-Electromechanical (NEM) Memory Cells,” IEEE Transactions on Nanotechnology, vol. 13, no. 6, pp.1102-1106, Nov. 2014. [SCI]

[73] Boram Han and Woo Young Choi, "Fringe Field Effects on Transient Characteristics of Nano-Electromechanical (NEM) Nonvolatile Memory Cells," Journal of Semiconductor Technology and Science, vol. 14, no. 5, pp. 609-614, Oct. 2014. [SCIE]

[72] Jae Hwan Han, Hyunjin Lee, Wansoo Kim, Gyuhan Yoon, and Woo Young Choi, "On-State Resistance Instability of Programmed Antifuse Cells during Read Operation," Journal of Semiconductor Technology and Science, vol. 14, no. 5, pp. 503-507, Oct. 2014. [SCIE]

[71] Ning Xi, Eou-Sik Cho, Woo Young Choi, and Il Hwan Cho, “ Disturbance characteristics of charge trap flash memory with tunneling field effect transistor,” Japanese Journal of Applied Physics, vol. 53, pp. 114201, Oct. 2014. [SCI]

[70] Jae Hwan Han, Kwanyong Kim, and Woo Young Choi, “ Bit-to-Bit Interference of Multi-Bit Nano-Electromechanical Memory Cells (T Cells),” IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 659-666, Jul. 2014. [SCI]

[69] Kwanyong Kim, Kwangseok Lee, Keun-Ho Lee, Young-Kwan Park, and Woo Young Choi, "A Finite Element Model for Bipolar Resistive Random Access Memory," Journal of Semiconductor Technology and Science, vol. 14, no. 3, pp. 268-273, Jun. 2014. [SCIE]

[68] Yong Jun Kim, Jun Geun Kang, Byungin Lee, Gyu-Seog Cho, Sung-Kye Park, and Woo Young Choi, “ Effects of Abnormal Cell-to-Cell Interference on NAND Flash Memory,” Japanese Journal of Applied Physics, vol. 53, no. 4S, pp. 04ED12, Mar. 2014. [SCI]

[67] Kwanyong Kim, Seong Jun Yoon and Woo Young Choi, “ Dual Random Circuit Breaker Network Model with Equivalent Thermal Circuit Network,” Applied Physics Express, Vol. 7, No. 2, pp. 024203-1- 024203-4, Feb. 2014. [SCI]

[66] Hyun Kook Lee and Woo Young Choi, "Linearity of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Journal of Semiconductor Technology and Science, vol. 13, no. 6, pp. 551–555, Dec. 2013. [SCIE]

[65] Chun Woong Park, Woo Young Choi, Jong Ho Lee, and Il Hwan Cho, "Reduction of ambipolar characteristics of vertical channel tunneling field effect transistor by using dielectric sidewall ," Semiconductor Science and Technology. vol. 28, no. 11, pp. 115022, Nov. 2013. [SCI]

 

[64] Eui-Young Song, Hwi Kim, Woo Young Choi, and Byoungho Lee, "Active directional beaming by mechanical actuation of double-sided plasmonic surface gratings ," Optics Letters , Vol. 38, no. 19, pp. 3827–3829, Oct. 2013. [SCI]


[63] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, and Byung-Gook Park, "Investigation on the Corner Effect of L-shaped Tunneling Field-Effect Transistors and Their Fabrication Method," Journal of Nanoscience and Nanotechnology, vol. 13, no. 9, pp. 6376-6381, Sep. 2013. [SCI]

[62] Byung Kyu Park, Woo Young Choi, Eou Sik Cho, and Il Hwan Cho, "Development of sacrificial layer wet etch process of TiNi for nano-electro-mechanical device application,"Journal of Semiconductor Technology and Science, vol. 13, no. 4, pp. 410-414, Aug. 2013. [SCIE]

[61] Kyoung Min Choi and Woo Young Choi, "Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs)," IEEE Electron Device Letters,vol. 34, no. 8, pp. 942-944, Aug. 2013. [SCI]

[60] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "L-shaped Tunneling Field-Effect Transistors for Complementary Logic Applications," IEICE Transactions on Electronics, vol. E96-C, no. 5, pp. 634-638, May 2013. [SCIE]

[59] Woo Young Choi, Min Su Han, Boram Han, Dongsun Seo, and Il Hwan Cho, "Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory," IEICE Transactions on Electronics, vol. E96-C, no. 5, pp. 714-717, May 2013. [SCIE]

[58] Gibong Lee, Jung-Shik Jang, and Woo Young Choi, "Dual-Dielectric-Constant Spacer Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Semiconductor Science and Technology, vol. 28, pp. 052001, Apr. 2013. [SCI]

[57] Jung-Shik Jang, Hyun Kook Lee, and Woo Young Choi, "Random Dopant Fluctuation Effects of Tunneling Field-Effect Transistors (TFETs)," Journal of the Institute of Electronics Engineers of Korea, vol. 49, no. 12, pp. 179-183, Dec. 2012.

[56] Woo Young Choi, "Development of a Nano-Electro-Mechanical Memory Simulator," Journal of the Institute of Electronics Engineers of Korea, vol. 49, no. 10, pp. 122-127, Oct. 2012.

[55] Min Jin Lee and Woo Young Choi, "'Effects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)," IEEE Electron Device Letters, vol. 33, no.10, pp 1459-1461, Oct. 2012. [SCI]

[54] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Design guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 51, no. 6, pp. 06FE09-1-06FE03-4, Jun. 2012. [SCI]

[53] Jae Sung Lee, Woo Young Choi, and In Man Kang, "Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 51, no. 6, pp. 06FE03-1-06FE03-5, Jun. 2012. [SCI]

[52] Gibong Lee and Woo Young Choi, "Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)," IEICE Transactions on Electronics, vol. E95-C, no. 5, pp.910-913, May 2012. [SCIE]

[51] Boram Han and Woo Young Choi, "Analytical Model of Nano-Electromechanical (NEM) Nonvolatile Memory Cells," IEICE Transactions on Electronics, vol. E95-C, no. 5, pp.914-916, May 2012. [SCIE]

[50] Kwangseok Lee and Woo Young Choi, "Multibit Operation of Nanoelectromechanical Memory Cells," IEEE Electron Device Letters,vol. 33, no.3, pp 309-311, Mar. 2012. [SCI]

[49] Kwangseok Lee, Jung-Shik Jang, Yongwoo Kwon, Keun-Ho Lee, Young-Kwan Park, and Woo Young Choi, "A Unified Model for Unipolar Resistive Random Access Memory," Applied Physics Letters, vol. 100, no. 8, pp. 083509, Mar. 2012. [SCI]

[48] Min Jin Lee and Woo Young Choi, “Dependency of Tunneling Field-Effect Transistor (TFET) Characteristics on Operation Regions,” Journal of Semiconductor Technology and Science, vol. 11, no. 4, pp. 287-294, Dec. 2011. [SCIE]

[47] Jung-Shik Jang and Woo Young Choi, "Ambipolarity Factor of Tunneling Field-Effect Transistors (TFETs)," Journal of Semiconductor Technology and Science, vol. 11, no. 4, pp. 272-277, Dec. 2011. [SCIE]

[46] In Man Kang, Jung-Shik Jang, and Woo Young Choi, "RF Performance of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 50, no. 12, pp. 124301-1-124301-4, Dec. 2011. [SCI]

[45] Woojun Lee and Woo Young Choi, "Influence of Inversion Layer on Tunneling Field-Effect Transistors," IEEE Electron Device Letters, vol. 32, no.9, pp 1191-1193, Sep. 2011. [SCI]

[44] Min Jin Lee and Woo Young Choi, “Distribution of post-breakdown resistance of MOSFETs," IEICE Electronics Express, vol.8, no.16, pp. 1309-1314, Sep. 2011. [SCIE]

[43] Min Jin Lee and Woo Young Choi, "Analytical Model of Single-Gate Silicon-on-Insulator (SOI) Tunneling Field-Effect Transistors (TFETs)," Solid-State Electronics, vol. 63, issue 1, pp. 110-114, Sep. 2011.[SCI]

[42] Woojun Lee and Woo Young Choi, "A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement," IEEE Transactions on Nanotechnology, vol. 10, no. 3, pp. 462-466, May 2011. [SCI]

[41] Seung Hyeun Roh, Kwangsoo Kim, and Woo Young Choi, "Scaling Trend of Nano-Electro-Mechanical (NEM) Nonvolatile Memory Cells Based on Finite Element Analysis (FEA)," IEEE Transactions on Nanotechnology, vol. 10, no. 3, pp. 647-651, May 2011. [SCI]

[40] Kwangseok Lee and Woo Young Choi, "Nanoelectromechanical Memory Cell (T Cell) for Low-Cost Embedded Nonvolatile Memory Applications", IEEE Transactions on Electron Devices, vol.58, no.4, pp. 1264-1267, Apr. 2011. [SCI]

[39] Woojun Lee, Kwangsoo Kim, and Woo Young Choi, "Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time," IEICE Transactions on Electronics, vol. E94-C, no. 1, pp. 110-115, Jan. 2011. [SCIE]

[38] Woo Young Choi and Woojun Lee, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 57, no. 9, pp. 2317-2319, Sep. 2010. [SCI]

[37] Woo Young Choi, "Characterization of surface forces for electro-mechanical memory cells," IEICE Electronics Express, vol. 7, no. 12, pp. 827-831, Jul. 2010. [SCI]

[36] Woo Young Choi, "Comparative Study of Tunneling Field-Effect Transistors and Metal–Oxide–Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 49, no. 4, pp. 04DJ12-1-04DJ12-3, Apr. 2010. [SCI]

[35] Woojun Lee and Woo Young Choi, "Quantitative Analysis of Hump Effects of Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 49, no. 4, pp. 04DC11-1-04DC11-3, Apr. 2010. [SCI]

[34] Woo Young Choi, "Applications of impact-ionization metal-oxide-semiconductor (I-MOS) devices to circuit design," Current Applied Physics, vol. 10, no. 2, pp. 444-451, Mar. 2010. [SCI]

[33] Woo Young Choi, "Design and Scaling of Nano-Electro-Mechanical Non-Volatile Memory (NEMory) Cells," Current Applied Physics, vol. 10, no. 1, pp. 311-316, Jan. 2010. [SCI]

[32] Woo Young Choi, "Three-Dimensional Stackable Electromechanical Nonvolatile Memory Cell (H Cell) for Four-Bit Operation," IEEE Electron Device Letters, vol. 31, no. 1, pp. 29-31, Jan. 2010. [SCI]

[31] Woo Young Choi, "A new method for stable numerical differentiation," Current Applied Physics, vol. 9, no. 6, pp. 1463-1466, Nov. 2009. [SCI]

[30] Jong Pil Kim, Jae Young Song, Sang Wan Kim, Jae Hyun Park, Woo Young Choi, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, “Self-Aligned Asymmetric Metal-Oxide-Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator,” Japanese Journal of Applied Physics, vol. 48, no. 9, pp. 091201, Sep., 2009. [SCI]

[29] Woo Young Choi, "Effect of Device Parameters on the Breakdown Voltage of I-MOS Devices," Japanese Journal of Applied Physics, vol. 48, no. 4, pp. 040203-1-040203-3, Apr. 2009. [SCI]

[28] Woo Young Choi and Tsu-Jae King Liu, "Reliability of Nano-Electro-Mechanical Non-Volatile Memory (NEMory) Cells," IEEE Electron Device Letters, vol. 30, no. 3, pp. 269-271, Mar. 2009. [SCI]

[27] Woo Young Choi, Taro Osabe, and Tsu-Jae King Liu, "Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling," IEEE Transactions on Electron Devices, vol. 55, no. 12, pp. 3482-3488, Dec. 2008. [SCI]

[26] Jong Pil Kim, Woo Young Choi, Jae Young Song, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, "Design and Fabrication of Asymmetric MOSFETs Using a Novel Self-Aligned Structure," IEEE Transactions on Electron Devices, vol. 54, no. 11, pp. 2969-2974, Nov. 2007. [SCI]

[25] Woo Young Choi, Byung-Gook Park, Jong Duk Lee and Tsu-Jae King Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less Than 60 mV/dec," IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, Aug. 2007. [SCI]

[24] Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, “Design and Simulation of Asymmetric MOSFETs”, IEICE Trans. Electron., vol. E90-C, pp. 978-982, May 2007. [SCI]

[23] Hoon Jeong, Yeun Seung Lee, Sangwoo Kang, Il Han Park, Woo Young Choi, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, "Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Strcucture," Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2143-2147, Apr. 2007. [SCI]

[22] Jae Young Song, Woo Young Choi, Jong Pil Kim, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, "Novel Gate-All-Around Metal-Oxide-Semicondurctor Field Effect Transistors with Self-Aligned Structure", Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2046-2049, Apr. 2007. [SCI]

[21] Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "Novel Tunneling Devices with Multi-Functionality," Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2622-2625, Apr. 2007. [SCI]

[20] Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, “Integration Process of Impact-Ionization Metal-Oxide-Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 46, no. 1, pp. 122~124, Jan. 2007. [SCI]

[19] Woo Young Choi, Byung Yong Choi, Dong-Won Kim, Choong-Ho Lee, Donggun Park, Jong Duk Lee, and Byung-Gook Park, "25-nm Programmable Virtual Source/Drain MOSFETs Using a Twin SONOS Memory Structure," Solid-State Electronics, vol. 50, issue 6, pp. 914-919, Jun. 2006. [SCI]

[18] Jae Young Song, Woo Young Choi, Ju Hee Park, Jong Duk Lee, and Byung-Gook Park, "Design Optimization of Gate-All-Around (GAA) MOSFETs," IEEE Transactions on Nanotechnology, vol. 5, no. 3, pp. 186-191, May 2006. [SCIE]

[17] Woo Young Choi, Jae Young Song, Jong Duk Lee, and Byung-Gook Park, "Effect of Source Extension Junction Depth and Substrate Doping Concentration on I-MOS Device Characteristics," IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1282-1285, May 2006. [SCI]

[16] Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices," Journal of Semiconductor Technology and Science, vol. 6, no. 1, pp. 43-51, Mar. 2006.

[15] Byung-Gook Park, Byung Yong Choi, Woo Young Choi, Yong Kyu Lee, Jong Duk Lee, Hyungcheol Shin, Suk-Kang Sung, Tae-Yong Kim, Eun Suk Cho, Byung Kyu Cho, Keun Hee Bai, Dong-Dae Kim, Dong-Won Kim, Choong-Ho Lee and Donggun Park, "Highly Manufacturable and Reliable 80-nm Gate Twin Silicon-Oxide-Nitride-Oxide-Silicon Memory Transistor," Jpn. J. Appl. Phys. vol. 44, pp. L 1214-L 1217, no. 39, Sep. 2005. [SCI]

[14] Woo Young Choi, Jae Young Song, Jong Duk Lee, Young June Park, and Byung-Gook Park, "A Novel Biasing Scheme for I-MOS (Impact-Ionization MOS) Devices," IEEE Transactions on Nanotechnology, vol. 4, no. 3, pp. 322-325, May 2005. [SCIE]

[13] Woo Young Choi, Jae Young Song, Jong Duk Lee, Young June Park, and Byung-Gook Park, "100nm N-/P-Channel I-MOS Using a Novel Self-Aligned Structure " IEEE Electron Device Letters, vol. 26, no. 4, pp. 261-263, Apr. 2005. [SCI]

[12] Woo Young Choi, Hwi Kim, Byoungho Lee, Jong Duk Lee, and Byung-Gook Park, "Stable Threshold Voltage Extraction Using Tikhonov’s Regularization Theory" IEEE Transactions on Electron Devices, vol. 51, no. 11, pp. 1833-1839, Nov. 2004. [SCI]

[11] Woo Young Choi, Dong Soo Woo, Byung Yong Choi, Jong Duk Lee and Byung-Gook Park, "Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization," Jpn. J. Appl. Phys. vol. 43, pp. 1759-1762, Part 1, no. 4B, Apr. 2004. [SCI]

[10] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Stable Extraction of Linearity (VIP3) for Nanoscale RF CMOS Devices," IEEE Microwave and Wireless Components Letters, vol. 14, issue 2, pp. 83-85, Feb. 2004. [SCI]

[9] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Reverse-Order Source/Drain with Double Offset Spacer Design Optimization for Sub-50-nm Low-Power MOSFETs," Journal of Korean Physical Society, vol. 44, no. 1, pp. 60-64, Jan. 2004. [SCI]

[8] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Reverse-Order Source/Drain Formation with Double Offset Spacer (RODOS) for Low-Power and High-Speed Application," IEEE Trans. on Nanotechnology, vol. 2, issue 4, pp. 210-216, Dec. 2003. [SCI]

[7] Dong-Soo Woo, Byung Yong Choi, Woo Young Choi, Myeong Won Lee, Jong Duk Lee, and Byung-Gook Park, "30 nm self-aligned finfet with large source/drain fan-out structure," IEE Electronics Letters, vol. 39, issue. 15, pp. 1154~1155, Jul. 2003. [SCI]

[6] Kyung-Hoon Chung, Woo Young Choi, Suk-Kang Sung, Dae Hwan Kim, Jong Duk Lee, and Byung-Gook Park, "Pattern multiplication method and the uniformity of nanoscale multiple lines," J. Vac. Sci. Technol. B. vol. 21, issues 4, pp. 1491-1495, July 2003. [SCI]

[5] Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Electrical Characteristics of FinFET With Vertically Nonuniform Source/Drain Doping Profile," IEEE Trans. on Nanotechnology, vol. 1, no. 4, pp. 233-237, Dec. 2002. [SCIE]  

[4] Woo Young Choi, Byung Yong Choi, Young Jin Choi, Dong-Soo Woo, Suk-Kang Sung, Jong Duk Lee and Byung-Gook Park, "Fabrication of a 30-nm Planar nMOSFETs Based on the Sidewall Patterning Technique," Journal of The Korean Physical Society, vol. 41, no. 4, pp. 497-500, Oct. 2002. [SCI]

[3] Kyung-Hoon Chung, Suk-Kang Sung, Dae Hwan Kim, Woo Young Choi, Cheon An Lee, Jong Duk Lee and Byung-Gook Park, "Nanoscale Multi-Line Patterning Using Sidewall Structure," Jpn. J. Appl. Phys. vol. 41, pp. 4410-4414, part 1, no. 6B, Jun. 2002. [SCI]

[2] Byung Yong Choi, Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "50nm MOSFETs with side-gates for induced source/drain extension," IEE Electronics Letters, vol. 38, no. 11, pp. 526~527, May 2002. [SCI]

[1] Woo Young Choi, Byung Yong Choi, Dong Soo Woo, Young Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Side-Gate Design Optimization of 50 nm MOSFETs with Electrically Induced Source/Drain," Jpn. J. Appl. Phys. vol. 41, part 1, no. 4B, pp. 2345-2347, Apr. 2002. [SCI]

  

 
Home | |